三維積體電路關鍵技術 於先進背照式感光元件應用之研究

Abstract

背照射互補示電晶體影像感應元件為下一世代的感光影像元件，相較於傳統的前面照射元件，背面照射有許多好處，像是減少雜訊、降低楊氏干涉現象、增加感光亮以及減少色彩的失真…等等。在現今的背面照射互補示電晶體影像感應元件的製程中大多會使用銅錫凸塊和點膠(underfill)兩種技術。銅錫凸塊被用來做為晶片和基板之間的電性連接，並且搭配點膠技術來提升其整體的可靠度。然而，由於銅錫凸塊接合技術在微縮上的困難，以至於限制了整個晶片的微縮。在本篇論文中提出縮減銅鎳錫接合的厚度，以達到次微米級的應用，並且配合其他三維積體電路關鍵技術:金屬接合及晶圓薄化技術，完成背面照射互補式電晶體影像感應元件的測試結構。為了確保在電性上的可靠度，我們在銅錫對銅錫凸塊的接合上進行克爾文測試結構(Kelvin test structure)及凸塊鏈接(daisy chain)的電性分析。而傳統的點膠，可能會在銅錫凸塊間留下許多的空洞及孔隙，在之後的可靠度測試中會造成相當程度的問題。因此，我們利用三維積體電路中的混合接合技術，使用其中的高分子部份取代了點膠，以解決點膠不完全所造成的可靠度問題。因此先研究其中的高分子接合作為前導研究，並以聚醯亞胺(polyimide, PI) 當作主要材料，研究聚醯亞胺的基本性質，並且利用材料分析和一連串的拉力及切割測試找出適合的接合條件並探討其機制。

Backside illumination CMOS image sensor (BSI-CIS) has many advantages such as reducing the noise beyond low illumination to lighten color distortion, enhancing the sensor current, and lowering the effect of Young's interference. Cu/Sn to Cu/Sn bump with under-fill is proposed to use in BSI-CIS fabrication. However, current Cu/Sn bump and under-fill technologies limit the scaling of the CIS chip. In this thesis, we reduce the Cu/Sn thickness successfully by novel Cu/Ni/Sn bonding and fabricate the test structure of BSI-CIS by wafer thinning and wafer bonding technologies. In addition, we evaluate the correspodning electrical characteristics and reliabilities in Kelvin test structure and daisy chain. On the other hand, during the under-fill filling, there are some issues like the micro-gap or voids between the Cu/Sn bumps. The concept of hybrid bonding can be used to solve these problems. In order to study the feasibility of hybrid bonding by Cu/Ni/Sn and polymer, we first evaluate polyimide dielectric bonding under different bonding temperature, and study the correlation between different parameters such as curing, time and temperature by FTIR. We also investigate the mechanical properties by pulling test and dicing test. These results of Cu/Ni/Sn bonding and polyimide bonding have provided the guideline for using hybrid bonding in BSI-CIS applications.