標題: | A Novel 3D Integration Scheme for Backside Illuminated CMOS Image Sensor Devices |
作者: | Ko, Cheng-Ta Hsiao, Zhi-Cheng Chang, Hsiang-Hung Lyu, Dian-Rong Hsu, Chao-Kai Fu, Huan-Chun Chien, Chun-Hsien Lo, Wei-Chung Chen, Kuan-Neng 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
關鍵字: | CMOS image sensor;backside illuminated;3D integration |
公開日期: | 1-六月-2014 |
摘要: | A novel backside-illuminated CMOS image sensor (BSI-CIS) scheme and process are developed and demonstrated. This innovative scheme can be realized without fusion oxide bonding and through-silicon via (TSV) fabrication. This wafer-level TSV-less BSI-CIS scheme includes transparent ultrathin silicon (similar to 3.6 mu m) and uses several bonding technologies. The characterization and assessment results indicate that the integration scheme possesses excellent electrical integrity and reliability. In addition, good quality results of the image functional test demonstrate the excellent performance of this scheme. This novel scheme also provides a realizable low-cost solution for the next-generation CIS and further 3-D novel BSI-CIS scheme. |
URI: | http://dx.doi.org/10.1109/TDMR.2014.2311887 http://hdl.handle.net/11536/24687 |
ISSN: | 1530-4388 |
DOI: | 10.1109/TDMR.2014.2311887 |
期刊: | IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY |
Volume: | 14 |
Issue: | 2 |
起始頁: | 715 |
結束頁: | 720 |
顯示於類別: | 期刊論文 |