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dc.contributor.author朱智安en_US
dc.contributor.authorJun, Chih-Anen_US
dc.contributor.author許騰尹en_US
dc.contributor.author朱智安en_US
dc.date.accessioned2014-12-12T02:38:41Z-
dc.date.available2014-12-12T02:38:41Z-
dc.date.issued2013en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#GT079955572en_US
dc.identifier.urihttp://hdl.handle.net/11536/73731-
dc.description.abstract這個論文實現了一個可調整式快速複利葉轉換器,支援802.15.3c以及802.11n兩種通訊規格。在802.15.3c規格下可最高支援到2.4 GS/s 取樣頻率,FFT點數可支援512、256、128 三種點數,而802.11n規格下可支援1、2、3、4 四種天線數,FFT點數可支援128、64 二種點數。 整體快速複利葉轉換器的架構是採用管線式並搭配Radix2、Radix22 演算法做再利用的規劃,來達到硬體利用率的上升以及硬體的節省。此外設計了可調整訊號量化噪聲比與動態控制電流搭配不同的通訊規格來節省功率上的消耗。zh_TW
dc.description.abstractThis thesis proposes and implements a reconfigurable Fast Fourier Transform (FFT) processor. The proposed reconfigurable FFT processor can support two types of wireless communication specifications, IEEE 802.15.3c and IEEE 802.11n. The support specification for 802.15.3c is 512, 256,128 three kinds of FFT points and the sampling rate of IEEE 802.15.3c is 2.4Gsample/s. And the support specification for 802.11n is 1, 2, 3, 4 four kinds of antenna numbers and 128, 64 three kinds of FFT points. The propose FFT use pipeline architecture and reuse architecture Radix2、Radix22 algorithm to reduce hardware cost and improve hardware utilization. In addition, we propose a dynamic current scaling (DCS) mechanism and muti-SQNR to achieve low power design.en_US
dc.language.isozh_TWen_US
dc.subject快速複利葉轉換器zh_TW
dc.subjectFFTen_US
dc.title多模式無線通訊應用下 高速8平行512點具有可變訊號量化噪聲比之 可調整式快速傅立葉轉換處理器zh_TW
dc.titleHigh Speed 8-Parallel 512-Point Reconfigurable FFT Processor with Scalable SQNR for Multi-mode Wireless Applicationsen_US
dc.typeThesisen_US
dc.contributor.department資訊科學與工程研究所zh_TW
Appears in Collections:Thesis