三五族金屬氧化物半導體場效電晶體應用之低阻抗金屬T型閘極與源/汲極接觸技術

Abstract

三五族材料與傳統矽相較，可提供較高的電子遷移率，在低操作電壓下，仍有高的載子漂移速率，可以達到良好的功率消耗與性能權衡取捨，非常有機會在將來取代矽通道材料，應用於低功耗的邏輯電路製作。 本論文探討可以應用於三五族的金屬氧化物半導體場效電晶體(MOSFET)的閘極與源/汲極技術以及結構製作與分析。 首先，閘極部分採用特殊的T-型金屬閘極結構，此種閘極截面其上方較寬廣的頭蓋部分讓RF訊號有較低阻抗的路徑，可以減少訊號強度在通過閘極時減弱，而閘極足部部分較頭部窄小，與基板接觸面積較小，形成較小的閘極長度，減少電子在通道的傳輸時間，增加操作頻率。為了製作更小的閘極線寬，我們利用氮化矽薄膜作為結構支撐層，加上”回蝕刻”(etch back)方法，達成閘極寬度縮小的目的，本篇論文之最小閘極寬度為60奈米。 源/汲極接觸技術是利用傳統金屬矽化物的概念，發展出自對準金屬合金結構，可應用在三五族磊晶層上，如砷化銦鎵、砷化鎵，此自對準方法可以降低元件寄生電阻值、縮小元件密度，並且可以減少使用微影曝光製程，達到節省成本及提升效能的目的。源/汲極接觸技術實驗，則設計多種不同金屬結構沉積在砷化銦鎵、砷化鎵上，探討經由不同溫度的退火所形成新的合金，其接觸電阻值的大小。實驗結果顯示鍺/鎳結構可達到最低的接觸電阻值為768 Ω∙um。利用上述所開發的閘極與源/汲極接觸技術，未來可應用於發展高效能的三五族金屬氧化物半導體場效電晶體技術。

III-V materials, comparing with Si, can provide significantly higher electron mobility and higher drift velocity under low voltage operation. Consequently, III-V materials are very promising to replace currently used Si as channel material in order to achieve a better power consumption/device performance tradeoff. In this thesis, gate and source/drain technologies for III-V metal oxide semiconductor field effect transistor (MOSFET) application have been developed. The related key structure fabrication as well as material and electrical analysis were also carried out in this study. Firstly, the control gate is basically a metal T-shaped gate structure consisting of (1) a wide top cover to provide a low-resistance path for RF signal passing through; (2) a narrow stem at the bottom as gate footprint to reduce the contact area with the substrate, to form smaller gate length, to reduce electron transit delay, and hence to increase operation frequencies. In order to achieve a smaller gate length, we use silicon nitride (SiNx) film as a structural support layer, coupled with "double nitride deposition and dry etching process" to shrink the gate length. The minimum finally gate length achieved in this study is 60 nm. Source/drain contact technology is developed based on conventional silicide technology which can be easily applied on III-V epitaxial layers, such as indium gallium arsenide and gallium arsenide, for self-aligned metal alloy formation. The self-aligned S/D structure without additional lithography steps can achieve better device density scaling and reduce the series resistance simultaneously. A variety of metal stacks were deposited on indium gallium arsenide or gallium arsenide substrates to form alloys under different annealing temperatures. Experimental results show that the lowest contact resistance achieved is 768 Ω∙um when using germanium/nickel metal contact stack. The developed gate and source/drain contact technologies are potential for future high-performance III-V MOSFET development.