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dc.contributor.authorHsiao, Jer-Minen_US
dc.contributor.authorTsai, Chun-Jenen_US
dc.date.accessioned2014-12-08T15:09:40Z-
dc.date.available2014-12-08T15:09:40Z-
dc.date.issued2007en_US
dc.identifier.isbn978-1-4244-0920-4en_US
dc.identifier.issn0271-4302en_US
dc.identifier.urihttp://hdl.handle.net/11536/7401-
dc.identifier.urihttp://dx.doi.org/10.1109/ISCAS.2007.377997en_US
dc.description.abstractDue to the variety of popular video coding standards, many efforts have been put into the design of a single video decoder chip that supports multiple formats. In 2004, ISO/IEC MPEG started a new work item to facilitate multi-format video codec design and to enable more flexible usage of coding tools. The work item has turned into the MPEG Reconfigurable Video Coding (RVC) framework. The key concept of the RVC framework is to allow flexible reconfiguration of coding tools to create different codec solutions on-the-fly. In this paper, flexible SoC architecture is proposed to support the RVC framework. Some analysis has been conducted to show the extra costs required for this platform compared to hard-wired codec architecture. In conclusion, the RVC framework can be mapped to an SoC platform to provide flexibility and scalability for dynamic application environment with reasonable cost in hardware design.en_US
dc.language.isoen_USen_US
dc.titleAnalysis of an SOC architecture for MPEG reconfigurable video coding frameworken_US
dc.typeArticleen_US
dc.identifier.doi10.1109/ISCAS.2007.377997en_US
dc.identifier.journal2007 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11en_US
dc.citation.spage761en_US
dc.citation.epage764en_US
dc.contributor.department資訊工程學系zh_TW
dc.contributor.departmentDepartment of Computer Scienceen_US
dc.identifier.wosnumberWOS:000251608401008-
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