奈米互補式金氧半製程下應用於射頻積體電路之靜電放電防護設計

Abstract

在現今的積體電路產業中，基於晶片整合度與成本的考量，射頻積體電路 (radio-frequency integrated circuits, RF ICs) 也逐漸傾向於實現在 CMOS 製程中。靜電放電 (electrostatic discharge, ESD) 是積體電路可靠度中最重要的一環，大多數電子產品的故障與損壞均與遭受靜電放電轟擊有關。由於射頻積體電路對於任何額外的寄生效應都相當敏感，因此能應用在射頻積體電路之靜電放電防護設計除了要有好的靜電放電耐受度之外，還必須要能將其寄生效應的影響降至最低。 在本篇論文首先提出了由傳統靜電放電防護設計修改並且無額外增加元件的新靜電放電防護元件設計。此新的設計採用堆疊的二極體 (diode) 並將矽控整流器 (silicon-controlled rectifier, SCR) 內嵌於其中並做為主要靜電放電之路徑。經由佈局優化能使得新的架構有更低的寄生電阻、低的寄生電容以及高的靜電放電防護能力，更適合做為晶片上的靜電放電防護設計。 本論文進一步將上述的靜電放電防護元件設計成可應用於差動式 (differential) 低雜訊放大器 (low-noise amplifier, LNA) 的靜電放電防護電路。由於在此靜電放電防護電路中，內嵌的矽控整流器是建立於一差動輸入端到另一差動輸入端之間，所以在兩輸入端之間 (pin-to-pin) 的靜電防護能力能夠提升。 此外，本論文進一步將靜電放電防護電路應用在 24 GHz 之低雜訊放大器電路以作驗證。根據量測結果，證明所提出的設計可以有效的提供差動低雜訊放大器電路出色的靜電放電防護能力以及良好的射頻電路性能。

For the consideration of high integration and low cost, radio-frequency integrated circuits (RF ICs) have been fabricated in nanoscale CMOS processes. Electrostatic discharge (ESD), which has become one of the most important reliability issues in IC products, must be taken into consideration during the design phase of all IC products. Since RF ICs are very sensitive to any extra parasitic effect, ESD protection design for RF ICs in nanoscale CMOS processes needs well ESD protection ability and small parasitic effect. In this thesis, the new ESD protection design which was modified from the conventional ESD protection design without adding any extra device has proposed. The new proposed ESD protection device utilizes stacked diodes with embedded silicon-controlled rectifier (SCR) as main ESD-current-discharging paths. The optimization on layout style of the stacked diodes is more suitable for on-chip ESD protection due to its low turn-on resistance, low parasitic capacitance, and high ESD robustness. The proposed ESD protection stacked diodes with embedded SCR has been also developed for the differential low-noise amplifier (LNA). The SCR path was established directly from one differential input pad to the other differential input pad, so the pin-to-pin ESD robustness can be improved. Besides, this design had been further applied to a 24-GHz LNA in the same CMOS process. Experimental results had shown that the proposed ESD protection design for the differential LNA can achieve excellent ESD robustness and good RF performances.