奈米尺度場效電晶體中電漿子引致長距庫侖效應之研究

Abstract

對未來數位元件的研發而言，了解奈米尺度載子的傳輸現象至關重要。本文從多晶矽閘極金氧半場效電晶體的遷移率研究出發，在不同溫度下進行n型長通道超薄氧化層電晶體的電性量測之後，先藉由研究團隊自建之量子計算模擬器準確標定電晶體特徵參數，進一步萃取出電子有效遷移率。經由比對來自文獻中的通用遷移率(universal mobility)與自建模擬器的遷移率模擬值之後發現，研究樣本中的通道表面粗糙度較文獻的厚氧化層樣本為低。在此前提之下，額外的散射機制必然存在。我們發現此額外散射機制的溫度相依性與文獻中的介面電漿子散射機制極為接近，且由文獻的理論計算結果可知，該機制可顯著影響遷移率的氧化層厚度亦與我們的研究樣本相符。穿透式電子顯微鏡照片的介面數位分析結果也支持此觀點。 接著針對同樣製程條件的元件樣本，我們延伸載子遷移率的研究至短通道元件中。考慮源/汲極效應的影響，在標定電晶體參數的工作上，我們採用技術型電腦輔助設計(TCAD)逆向模擬的方式，在各項參數沿用調校過的廠設值的條件之下，擬似在不同溫度下量測得到的電流-電壓特性，藉以得到近似的摻雜分布。最終目的是希望得到可靠的元件參數，諸如反轉層電子密度、源/汲極電阻等等，進而獲取真確的電子有效遷移率。經由一系列的分析，我們認為通道長度小於50奈米的短通道元件中，關建的額外散射機制以遠距(remote)庫侖散射與長距(long-range)庫侖效應為主，且在30奈米左右的尺度，後者的主導性將超過前者。 在長距庫侖效應的模擬分析中，我們創新應用機率分布的概念進入薛丁格-波以松自洽模擬過程，探討電位擾動的現象。除了載子均溫上升外，臨界電壓的微幅下降及遷移率的明顯降低均可從我們的模擬分析結果中看見。因為載子增溫，使得短通道元件中載子速度過衝的現象受到緩和，是效能提升的一大障礙。考慮此效應，我們針對未來世代場效電晶體，以雙閘極的結構為藍本，透過合併使用技術型電腦輔助設計的水動力學(HD)與漂移擴散(DD)傳輸模型得到飽和驅動電流的預測。我們認為，為了滿足國際半導體技術藍圖(ITRS)高效能元件的的設計標準，應力施加和源/汲極電阻的有效下降，是持續以矽作為通道材料的兩大條件。

For future device design and manufacturing, understanding of carrier transport in nano scale is stringent. Study on effective mobility extracted from a polysilicon gate metal-oxide-semiconductor field-effect-transistor at different temperatures serves as a starting point of this research. For an ultra-thin gate-oxide nMOSFET, device parameters are characterized through our in-house Schrödinger-Poisson self-consistent quantum simulator and measured electrical characteristics. Then electron effective mobility can be straightforwardly determined and further analyzed. It is found that the surface roughness of the sample under study is smaller than published values for thick-oxide devices. Through temperature dependent analysis, interface plasmon scattering is expected to be the dominant extra scattering mechanism while other candidates are ruled out. Further TEM digitization analysis supports the conclusion for a smoother interface. Second, we extend the mobility analysis to transport study in short channel devices. To take short-channel effect into account, a TCAD inverse modeling technique is utilized. After obtaining the device parameters such as inversion charge density and series source/drain resistance, effective mobility may be determined for further analysis. Within tolerable error margin for application of Matthiessen’s rule, temperature dependence is again examined to identify dominant scattering mechanism. After excluding other possible mechanisms, the remote-Coulomb-scattering and long-range Coulomb effect originating from highly-doped source/drain plasmon excitation are suspected to play significant role in carrier scattering within very short channels. The latter is found to dominate over the former for channel shorter than around 30 to 40 nm. From simulation analysis of long-range Coulomb effect, potential fluctuation within channel is proposed to be simulated through weighted Schrödinger-Poisson self-consistent process. The result shows that both potential fluctuation and carrier heating may bring to mobility degradation. Furthermore, threshold voltage roll-off is also expected. On the other hand, carrier heating is directly linked to the reduction of velocity overshoot since higher electron temperature results in a smaller momentum relaxation time. From such perspective, saturation current drive is predicted for future nodes by the combined usage of TCAD hydrodynamic and drift-diffusion model. It is finally concluded that both strained-Si technology and series source/drain resistance shrinkage are essential for the continuing adoption of Si channel under the requirement of ITRS high-performance standard.