先進High-k/Metal Gate之金氧半場效電晶體 電性分析與可靠度研究

Abstract

經過多年的發展與研究，高介電係數(high-k)絕緣層取代傳統SiO2絕緣層是一種有效的方式去解決閘極漏電問題，特別是HfO2。HfO2已經量產於通道長度32nm或更小尺寸的元件，HfO2在最近幾年已經被廣泛的研究，儘管如此，許多量測技術必須修正，尤其是charge pumping(CP)量測技術，而charge pumping量測技術在偵測缺陷方面扮演重要的角色。 因此我們在第一部分主要針對charge pumping量測技術在30Å厚的HfO2絕緣層n-channel MOSFETs中的異常缺陷，藉由排出載子時間公式和穿隧時間與距離的關係式，這異常缺陷可以被證實是高介電係數HfO2絕緣層中的淺缺陷，更進一步觀察HfO2絕緣層中的缺陷貢獻在charge pumping電流的行為，不同氮濃度TixN1-x金屬閘極與不同介面層(interlayer)厚度元件做個比較，從這些比較顯示出異常缺陷出現只有在當通道電子注入到高介電係數絕緣層缺陷中，接著由排出載子時間公式和不同波降時間(tfalling time)，結果顯示電子先從高介電係數絕緣層淺缺陷逃離到通道中，此時電子會先流入源極與汲極中，此電流不會貢獻到ICP，在波谷時間(tbase level)剩餘的電子會流入基極進而貢獻到ICP，結合以上的結論，在低閘極電壓時，閘極電流是由穿隧路徑主導，ICP偵測到介面缺陷和幾何電流，相反的，在高閘極電壓時，閘極電流是由Frenkel-Poole機制主導，ICP偵測到三種電流，分別是介面缺陷、幾何電流和高介電係數HfO2絕緣層中的淺缺陷。 第二部分顯示charge pumping量測技術在較高電壓30Å厚的HfO2絕緣層p-channel MOSFETs量到異常缺陷，透過分流法與機制擬合可以確認初始的電流機制是Frenkel-Poole機制，藉由排出載子時間公式和穿隧時間與距離的關係式，這異常缺陷可以被證實確實是高介電係數HfO2絕緣層中的淺缺陷。 第三部分顯示輸入/輸出(I/O) TiN/HfO2 n-MOSFETs在正偏壓劣化(PBS)後使用快速量測發現截止電壓(Vt) 朝異常的負方向移動，在9次PBS與恢復之後，VT幾乎完全恢復，這結果顯示這過程是可逆的，而由微小的閘極電流和來回掃的快速量測得知在PBS之後電子由高介電係數HfO2絕緣層中的缺陷逃出至金屬閘極，導致VT下降，反之，在施加恢復電壓(Vrecovery)時間，電子從金屬閘極注入到高介電係數HfO2絕緣層中的缺陷，導致VT上升，透過機制擬合得知斜率是-1，因此捕獲和排出載子過程已被證實是穿隧機制，此外輸入/輸出元件(I/O device)與標準元件(standard device)在PBS後，Vt移動方向是相反，因為在I/O device從HfO2絕緣層的缺陷逃出，在standard device通道電子注入HfO2絕緣層中的缺陷，根據以上的結果，透過減少預存在的HfO2絕緣層中的缺陷，發射/捕獲效應(charge/discharge effect) 可以被減少，例如：摻雜Zr到HfO2絕緣層中。 最後，異常的閘極漏電流波包被觀察到在動態和靜態負偏壓劣化(dynamic negative bias stress；dynamic NBS and negative-bias temperature-instability；NBTI)在HfxZr1-xO2 and HfO2金屬閘極P型金氧半場效電晶體之後，這個結果歸因於電動被捕獲在高介電係數絕緣層中，機制擬合顯示在dynamic NBS和NBTI之後，當Vg小於Vt閘極漏電流機制從Frenkel-Poole機制轉為Tunneling機制是因為E high-k > E sio2，當Vg大於Vt閘極漏電流機制從Tunneling機制轉為Frenkel-Poole機制是因為E high-k < E sio2，這些異常的現象歸因於電場須遵守E high-k εhigh-k = Q + Esio2ε sio2這個式子。接著，從有摻雜Zr和沒摻雜Zr經過動態負偏壓劣化後的比較，我們發現閘極漏電流波包產生條件需要足夠多的電動補獲到high-k絕緣層中和較大初始值的閘極漏電流，這些結果皆遵守波包的產生的條件JTunneling << JFrenkel-Poole。

Many years of research and development has shown that one valid way to solve problems of gate leakage current is that replacing conventional SiO2 gate dielectric with high-k dielectric, especially with HfO2 gate dielectrics. HfO2 gate dielectrics have been implemented at the 32nm technology node and smaller. Nevertheless, many measurement techniques must be refined, especially charge pumping techniques playing an important role in inspection of defects. Consequently, the first part mainly focuses on abnormal traps measured by the charge pumping technique for 3nm HfO2 dielectric n-MOSFETs in high gate voltage. It can be verified the abnormal traps being high-k bulk shallow traps by fitting the discharge time formula and the related formula between tunneling time and distance. To further investigate the behavior of these additional traps contributing to charge pumping current, devices with different interlayer thicknesses and different N concentrations in the TixN1-x metal gate are compared. These comparisons show that abnormal traps appear only when channel electrons inject to high-k bulk shallow traps. Subsequently, by fitting discharge formula for different tfalling time, results show that electrons escape from high-k bulk shallow traps first to the channel and then to source and drain during tfalling time. This current cannot be measured by the charge pumping technique. Subsequent measurements of NT by charge pumping technique at tbase level reveal a remainder of electrons trapped in high-k bulk shallow traps. Combining with results above, gate current is tunneling-path dominated in low Vg, and Icp detects interface trap (Nit) and “geometrical component” of Icp (Ncp,gc). On the contrary, the gate current is dominated by the Frenkel-Poole mechanism in high Vg, and Icp measures Nit, Ncp,gc, and Nhkst (high-k bulk shallow trap). The second part exhibits the extra amount of NT contributes to charge pumping current in high voltage regime in p-channel MOSFETs. Via distinguish current and current fitting, it is confirmed that initial gate current is Frenkel-Poole mechanism. Via fitting discharge formula with different temperature and related formula between tunneling time and distance, dHfO2,trap can be calculated to be 13.2Å ~ 16.2Å. This result is versified that extra Icp traps is actually located in the high-k bulk shallow traps in p-channel MOSFETs. The third part shows abnormal negative threshold voltage shifts under positive bias stress in input/output TiN/HfO2 n-MOSFETs using fast I-V measurement. After nine cycles of stress and recovery, Vt almost completely recovers. This result demonstrates that this process is reversible. The fast I-V double sweep measurement with insignificant gate current indicates that electrons escape from high-k bulk traps to the metal gate in Vhigh level, leading to a decrease in Vt. On the contrary, electrons inject from the metal gate to high-k bulk traps in Vbase level, causing an increase in Vt. Through curve fitting, the charge/discharge process is confirmed via the tunneling mechanism due to -1 in value in the slope. In addition, the direction of Vt shift in input/output (I/O) device is contrary to that in the standard performance device since electrons escape from high-k bulk traps to metal gate by the tunneling mechanism in I/O device rather than channel electrons injecting to bulk traps, owing to the large interlayer thickness. According to these results, the charge/discharge effect is reduced with a decrease in pre-existing high-k bulk traps, such as employing Zr doping in HfO2 dielectric device. Finally, an anomalous gate current hump is observed after dynamic negative bias stress (NBS) and negative-bias temperature-instability (NBTI) in HfxZr1-xO2 and HfO2/metal gate p-channel metal-oxide-semiconductor field-effect transistors. This result is attributed to hole trapping in high-k bulk traps. Fitting gate current after dynamic NBS and NBTI indicates that JFrenkel-Poole changes to JTunneling when Vg < Vt owing to the influence of E high-k > E sio2, while JTunneling changes to JFrenkel-Poole when Vg > Vt due to the influence of E high-k < E sio2. These phenomena can be attributed to the fact that the electric field must follow the formula E high-k εhigh-k = Q + Esio2ε sio2. Subsequently, from Zr-undoped and Zr-doped devices after dynamic NBS, we conclude that the gate current hump requires both sufficient hole trapping and larger initial gate current. Moreover, Zr-doped devices can ameliorate dynamic NBS and NBTI. These results obey the hump generation condition JTunneling << JFrenkel-Poole.