40 GHz共平面波導對共平面波導熱導孔高頻轉接之研究

Abstract

摘 要

IC性能大部分仰賴晶片內部元件尺寸的微小化，傳統晶片與基板間藉由打線接合（Wire Bonding）為訊號傳遞之方式，已成為高速高性能IC發展的瓶頸。因此，業界採用高密度化的覆晶接合方式取代傳統打線接合 [1]，而覆晶封裝在砷化鎵微波通訊元件中已經廣泛的被應用與研究。 近來，德國的 Ferdinand-Braun-Institute (FBH) 實驗室提出一種新穎結構 - Hot-Via Flip-Chip Interconnect [2]。傳統覆晶封裝結構之晶面的 Active Region 是朝下的，而 Hot-Via Interconnect 之晶片的 Active Region 是朝上的，所以正面的 Active Region 必須藉由穿過晶片的金屬連線連到晶面背面。此結構有兩個優點：第一，封裝之後，晶片的正面可以容易地被檢測；第二，因為晶片的正面是朝上的，且晶片背面的金屬線，可以當作晶片 Active Region 跟基板線路間的屏壁結構，可減少之間交互作用所產生之 detuning effect 。此結構之晶片正面的金屬墊需要跟背面的線路作連接，因此我們必須藉由砷化鎵元件的後段製程來達到我們的目的，因此也增加了製程的困難度。我們可將 Hot-Via Interconnect 視為是覆晶封裝跟砷化鎵元件後段製程的結合。砷化鎵元件的後段製程需將砷化鎵晶片薄化至100~150μm，然後蝕刻引洞（Via hole），接下來再佈上金屬線路（Metallization），使背面能跟正面的金屬墊連結。而此結構之金屬凸塊（Bumps）是長在基板之上，藉由Hot-Via封裝之後，晶片跟基板可構成金屬連線，以達成封裝之目的。 本研究內容分為兩部分：第一部分為被動的 CPW-to-CPW hot-via傳輸線路之模擬設計，第二部分是其製程之研究發展，希望製作之結構可以運用在頻率 40 GHz 以上。

Abstract

The performance of the integrated circuits is mainly dependent on the minimization of the size. Traditional wire bonding has restrictions on high speed and high frequency integrated circuits performance. Therefore, flip-chip bonding technology was used in industry to replace traditional wire bonding for high density packaging [1]. Moreover, flip-chip bonding has been widely applied on the research for GaAs microwave device packaging. Recently, a new structure – “Hot-via flip-chip interconnects” was introduced by the Ferdinand-Braun-Institute (FBH) in Germany [2]. The active region of traditional flip-chip is face-down, however, the active region is face-up in the hot-via interconnect structure. Thus the front side of active region has to be connected to the backside through metalized via-holes penetrating the substrate. There are several advantages for this structure： Firstly, the chip can be optically inspected after bonding； secondly, because the chip is face-up, the backside metallization can act as a shielding structure to separate the front active region from the substrate metal circuits. Therefore, it can reduce the detuning effect, caused by the interactions between circuits in the active region and on the substrate. Since the front-side metal pads have to be connected to the back-side metallization, we must develop the GaAs backside process to achieve our goals. Thus the process is more difficult and complicated. We can take hot-via interconnect as the combination of flip-chip bonding and GaAs backside process. The steps of GaAs backside process is described here. In the beginning, the chip has to be thinned to about 100μm~150μm. Then, we accomplished the via hole etching process by ICP. Finally, Backside metallization by electro plating was performed to connect the front-side to the back-side. In this study, the bumps of this structure were grown on the substrate side. After hot-via packaging, the chip and substrate were connected by metal interconnection for packaging purpose. There are two parts included in this research: The first part is the design and the simulation of the CPW-to-CPW hot-via passive transition structure. And the second part is the fabrication of the structure. The goal of this research is to provide a hot-via interconnect structure for applications up to 40 GHz.