薄膜形貌工程薄膜電晶體之單極性反向器之設計與製造

Abstract

在本篇論文中，我們首度嘗試以本實驗室新開發之薄膜形貌工程薄膜電晶體進行反向器電路之製作。我們採用電阻式負載與電晶體式負載兩種反向器電路，其中電晶體式負載須將負載之閘極與電路之輸出端相連接。我們有意的利用薄膜形貌工程薄膜電晶體特殊的短通道效應，達到控制反向器之電壓傳輸曲線的效果。而在整個電路的製程中最主要的問題為，如何在電路輸出端之接觸窗區域有效的連接負載電晶體之閘極與源極，使反向器能正確的工作並提升電路整體之良率。為解決此問題，我們在接觸窗之微影步驟採用過曝的方法形成圖案，且在後續的金屬沉積之前先以感應耦合電漿梨子蝕刻系統清潔表面之氧化層。而藉由實驗結果的比較，我們也確認了以上兩種方法確實有助於解決接觸窗區域之連接問題。 在本篇論文中，我們同時討論了單科薄膜電晶體以及其相對應的反向器電路之特性。在單科元件特性上，我們觀察到了當元件之通道長度從0.5微米增加到1微米，其臨界電壓將有0.768伏特之偏移量。而在反向器電路方面，在同樣操作於五伏特之情形下，電阻式負載電壓增益之峰值將近5，而電晶體式負載電壓增益之峰值則達到28。同時我們也對元件尺寸對於反向器電路之電壓傳輸曲線之影響，以及此優異之電壓增益的原因進行探討。最後我們對元件新發現之結構與製程上之問題進行探討，並提出一些可能的解決辦法。

In this paper, for the first time, we use the novel FPE TFT structure developed by our group recently to realize the inverters. We adopt two types of inverters. One is using a resistor as the load. The other is using a transistor as the load, and the gate of the load transistor is connected to the output node of the inverter. The channel length effect of FPE TFT is intentionally modulated to adjust the transition of the VTC. The major problem of the process is to connect the gate of the load-resistor and source electrodes at the contact (output node) region. To improve the yield of the inverters, a modification in process steps by adding an over-exposure and an ICP pre-clean step prior to the metal deposition is adopted to solve the connection problem. The solved contact problem is confirmed from the performance of the inverters. Characteristics of TFTs and associated impacts on the performance of inverters are investigated and discussed. For the short channel effect of FPE TFTs, a 0.768V VTH shift is observed as the channel length increases from 0.5μm to 1μm. The peak voltage gain is about 5 for the resistor-load inverters and 28 for the transistor-load inverter at operation voltage of 5V. Trends of the VTC shift with the device’s dimension and the origin of such excellent voltage gains of the inverters are investigated. At last, some issues presenting in device structures and fabrication, and the possible solution are also addressed.