高速與低功率邏輯應用之砷化銦鋁/砷化銦鎵變異結構高電子移動率電晶體之研究

Abstract

本研究成功製作高頻與低功率邏輯應用之高效能砷化銦鋁/砷化銦鎵變異結構高電子移動率電晶體 (Metamorphic High Electron Mobility Transistors，MHEMTs)，並且對此元件做了深入的分析與探討。為了增進此變異結構高電子移動率電晶體之特性，在改善元件磊晶結構的同時，也搭配了奈米級閘極線寬與白金閘極掘入 (Pt-buried gate) 的技術。另外，也對未來N型金氧半場效電晶體極具潛力的三五半導體通道材料其表面處理方式做了詳細的探討。 在論文中，研發出以白金閘極掘入的技術應用在以砷化銦 (InAs) 為通道的HEMT元件上。利用此方式有許多的優點，白金的功函數較傳統以鈦金屬閘極高，在掘入蕭基特層後，不但可以縮短電極與通道間距離，藉以抑制短通道效應外，還可以降低漏電流與源極阻抗等等，進而改善微波與邏輯特性。用此方法製作的HEMT元件具有1418 mA/mm的汲極-源極電流以及1600mS/mm的高轉導值。此元件與未有閘極掘入元件相較下，截止頻率(fT)由原本的390 GHz提升到494 GHz，最大震盪頻率(fmax)也由原本的360 GHz提升到390 GHz。在雜訊指數方面，在17 GHz頻率下為0.82 dB且相對應的增益(associated gain)為14 dB，其量測的汲極偏壓為0.3V而直流消耗功率僅1.14 mW，顯現此元件極有潛力作為低電壓的小訊號放大器，此外由於閘極掘入後，閘極漏電與閘極-源極電容值皆變小，使得在元件閘極延遲時間上達到0.78 picosecond且其開關電流比值依舊維持在三個數量級。 另外，更進一步的縮小源極與汲極間距，期使元件的邏輯特性更加優異，並且成功的應用在HEMT元件製作上，同時也分析了這種窄能隙半導體其撞擊離子化的現象並與先進的矽半導體元件及砷化銻(InSb)元件做了詳細的比較與邏輯特性分析。此砷化銦為主通道，銦含量高達70%的砷化銦鎵為次通道的元件，其發生撞擊離子化偏壓點約為0.8 V左右。在邏輯特性方面，此元件的汲極引致能障下降為200mV/V，次臨界擺幅約115 mV/dec，在偏壓0.5 V時展現了0.54 picosecond的閘極延遲，但由於其通道為窄能隙半導體，關閉態的漏電流較大，起因於蕭基特閘極漏電與能帶能帶間的穿遂電流，但相較於砷化銻通道元件佳。此外，與先進的矽奈米元件相比，砷化銦通道HEMTs展現了優異的閘極延遲與3.1倍高的fT於相同直流消耗功率上等特性。因此，III-V 高速元件將會是在後矽半導體世代扮演重要的角色。 另外，論文中也探討了以10 奈米厚的二氧化鋯高介電常數材料製作的假晶砷化銦鎵(In0.53Ga0.47As)金氧半電容結構。在成長介電薄膜時砷化銦鎵的表面也做了以硫化銨與稀釋鹽酸處理。比較兩者之後發現，經過硫化處理與350度退火後的電容結構具有良好的電容-電性特性(強反轉現象)，高崩潰電壓，與低漏電等，可見其具有較低的介面缺陷或是較少的不完美鍵結因而減低了費米釘札(Fermi-level pinning)。由材料分析得知，在高解析度的穿透式電子顯微鏡下可看到約20Å的薄膜介於半導體與介電薄膜中，進一步透過二次離子質譜儀分析，此薄膜為硫元素。因此證明了以硫化銨處理後其可以保護三五半導體表面發生原生氧化層導致元件特性變差。

High performance eighty nanometer gate length InAlAs/InxGa1-xAs metamorphic high electron mobility transistors (MHEMTs) have been fabricated successfully and characterized for high frequency and low-power logic applications. The performance of the MHEMTs was improved by optimizing the device structure, using the Pt-buried gate techniques and shrinking the source-drain spacing. In addition, the surface pre-treatments of III-V channel material before high-k deposition for future III-V nMOSFET were also studied. In this dissertation, the fabrication of 80 nm InAs channel MHEMTs using Pt gate-sinking was developed. There are several advantages to improve RF and logic performance with gate-sinking process such as high metal work function, suppression the short channel effect, the reduction of the gate leakage current and decrease of the source resistance. The fabricated InAs MHEMT using this technique shows a drain-source current of 1418 mA/mm and transconductance of 1600 mS/mm. The cutoff frequency fT and maximum oscillation frequency fmax of the MHEMT with Pt-buried gate are 494 GHz and 390 GHz as compared with that of 390 GHz and 360 GHz for device without gate sinking, respectively. The noise figure of the InAs MHEMT was 0.82dB and the associated gain was 14 dB at 17GHz under the bias condition of VDS = 0.3 V, indicating great potential for low-power LNA application. Because of the reduction of gate leakage current and gate-to-source capacitance, the intrinsic gate delay of the device is 0.78 picosecond, while maintaining an ION/IOFF ratio above 103. In addition, to promote the logic performance of InAs HEMT, device with small source-drain spacing were fabricated for high speed and low-voltage digital applications. Care must be taken while biasing device with such narrow energy bandgap when the impact ionization occurred in order to avoid the degradation of devices. Performance degradations were observed on the DC and RF characteristics due to impact ionization when the drain bias VDS > 0.8 V. For logic parameters, a drain-induced barrier lowering of 200 mV/V, a subthreshold slope of 115 mV/dec and a very low gate delay of 0.54 ps were obtained. Besides, InAs HEMTs exhibit excellent logic performances such as gate delay and 3.1 times higher fT at the same DC power dissipation when benchmarking advanced Si MOSFETs. Therefore, III-V high speed device has great potential to play an important role in Post-Si era. In addition, the electrical properties of the metamorphic In0.53Ga0.47As metal-oxide-semiconductor capacitors with a 100-Å-thick ZrO2 layer as high-k dielectrics were investigated. The In0.53Ga0.47As surface was pretreated by either sulfur passivation or HCl cleaning before the ZrO2 deposition. Owing to the lower interface-state density or Fermi-level unpinning after sulfidation, the sulfur-passivated capacitor exhibited better accumulation capacitance and strong inversion at capacitance-voltage measurement than the HCl-cleaned capacitor after post deposition annealing at 350 oC. On the basis of material analyses including High Resolution TEM and Secondary Ion Mass Spectrometer, the capacitors that subjected to sulfur treatment were found to contain a thin sulfur layer on the interface, which protects the surface from oxidation and prevents performance degradation.