利用單電晶體之多位元電阻式記憶體於低成本嵌入式應用

Abstract

電阻式隨機存取記憶體 (resistive-switching random access memory, RRAM) 近年獲得廣泛重視，被視為下一世代非揮發性記憶體 (nonvolatile memory, NVM) 應用的選擇之一。其具有許多的優點，例如：簡單的元件結構、較低的操作電壓、快速的切換速度以及較高的整合密度。然而，在嵌入式記憶體應用上，傳統的金屬-絕緣層-金屬(metal-insulator-metal, MIM) 結構僅能適用於後段製程，因此無可避免地會增加製程步驟與光罩需求，進而提高製造成本。為了要符合低成本嵌入式記憶體的需求甚至達成面板系統整合 (system-on-panel, SOP) 或是軟性電子系統整合(system-on-plastic, SoP) ，我們相信電阻式記憶體元件與前段電晶體的相互整合，能以最低成本實現嵌入式非揮發性記憶體。在本論文當中，我們提出且研究兩種記憶體元件，分別根據與邏輯製程相互匹配之低溫複晶矽薄膜電晶體 (LTPS-TFT) 及非晶氧化銦鎵鋅薄膜電晶體 (-IGZO TFT) 結構實現低成本嵌入式記憶體應用。 首先，我們提出利用低溫複晶矽薄膜電晶體，搭配二氧化鉿與鎳金屬閘極之新穎二位元 (two-bit-per-cell) 嵌入式非揮發記憶體。其優點為在現階段邏輯製程技術上不需要額外的光罩以及額外製程步驟。單一電晶體可分別利用汲級與源級各自獨立且局部的電阻切換實現二位元操作，相較於現階段單一複晶矽 (single-poly) 非揮發性記憶體，提供了更多的位元數目，進而達到低成本之嵌入式應用。除此之外，在電阻式切換後，可忽略的電晶體特性劣化現象則允許在單一元件上達到可轉換之邏輯及記憶體雙重特性。 接著，根據在單一低溫複晶矽薄膜電晶體上實現可轉換邏輯及記憶體操作的概念，利用不同的操作模式獲得電晶體與電阻式切換之最佳條件。根據實驗結果，無論是電阻式切換的位置以及由電荷捕捉 (charge trapping) 所造成的臨界電壓 (threshold voltage, VTH) 偏移，都與操作方式有強烈的關係。汲極偏壓模式 (drain-biased mode) 具有比閘極偏壓模式 (gate-biased mode) 更好的表現，原因是無論電阻式切換或是電荷補捉都可被限制在閘極與汲極交錯 (gate/drain overlap) 的區域。而雙極性切換模式 (bipolar RS mode) 則可以提供額外的好處，例如當元件切換至高阻態 (high resistance state) 時，電晶體會有較低的關閉電流。利用汲極偏壓雙極性切換模式，經過電阻式切換後，所造成的劣化程度將會是最小的，因此可以有效達到可轉換的邏輯及記憶體雙重特性。除此之外，由於在汲極與源極端可以實現互不影響且各自獨立的電阻式切換，可以達到單一電晶體中二位元高密度資料儲存。 在論文的最後，我們展示兩種高位元密度可撓式非揮發性記憶體技術，其利用與邏輯技術互相匹配之低溫非晶氧化銦鎵鋅薄膜電晶體結構所完成。經過電性形成 (electrical forming) 前，非晶氧化銦鎵鋅薄膜電晶體具有非常良好的電晶體特性，在經過電性形成後，根據不同結構的非晶氧化銦鎵薄鋅膜電晶體，利用其在汲級端與源極端獨立且多阻態特性，可在單一電晶體結構中，實現二位元及三位元 (three-bit-per-cell) 之電阻式記憶體。結合邏輯與記憶體雙重功能、低製程溫度、低整合成本、高位元密度以及絕佳的可撓式記憶體特性，所提出的元件在未來軟性電子系統整合應用上非常具有潛力。我們相信此篇論文的研究成果可以提供未來嵌入式記憶體一種全新的選擇。

Resistive-switching random access memory (RRAM) has garnered significant interest for next-generation nonvolatile memory (NVM) applications because of numerous advantages including its simple cell structure, low operational voltage, fast switching speed and high integration density. However, the conventional metal-insulator-metal (MIM) structure can only be implemented into the CMOS backend processes for embedded memory applications, which inevitably require additional process steps and masks, and thus further increase manufacturing cost. To meet the requirement of low-cost embedded NVM technology for system-on-panel (SOP) or system-on-plastic (SoP) applications, we believe that integrating the RRAM cells with the frontend transistors is an attractive solution. In this dissertation, two types of RRAM cells are proposed and investigated using logic-compatible low-temperature poly-Si thin-film transistor (LTPS-TFT) and amorphous indium-gallium- zinc-oxide TFT (-IGZO TFT) for low-cost embedded memory applications. Firstly, a novel two-bit-per-cell embedded nonvolatile memory requiring no additional masks and process steps in a logic process technology has been proposed using a LTPS-TFT with a HfO2/Ni gate stack. A two-bit-per-cell operation can be realized in a single transistor by using independent, localized resistive switching at the drain and source bits, respectively, and renders higher bit-density as compared with the present single-poly embedded nonvolatile memory. Furthermore, negligible degradation of the transistor characteristics after resistive switching allows interchangeable logic/memory operations in an identical device. Then, various operating modes have been investigated for optimal transistor and resistive switching (RS) characteristics in the interchangeable logic/memory LTPS-TFT. Both the RS location and the device threshold voltage (VTH) shift caused by charge trapping depend strongly on the operating modes. The drain-biased mode is superior to the gate-biased mode because both the RS and charge trapping can be confined in the localized gate/drain overlapped region. The bipolar RS mode provides an additional advantage of lower off-state current as the transistor resetting back to its high resistance state. By using the drain-biased bipolar RS mode, the transistor degradation after RS can be minimized to enable interchangeable logic/memory functions. In addition, because RS can be operated independently at the drain and source bits without significant programming interference, two-bit-per-cell operation can be achieved in a single transistor for high-density data storage. Finally, we demonstrate two types of flexible nonvolatile memories with high bit-density by using logic-compatible -IGZO TFTs fabricated at low temperature. Before electrical forming, the -IGZO TFTs exhibit excellent transistor performance. After electrical forming, two-bit-per-cell and three-bit-per-cell resistive-switching memories are realized using localized multilevel resistance states at the drain and source bits in different -IGZO TFT structures. Combining dual functionalities, low-temperature fabrication, low-cost integration, high bit-density, and excellent flexible memory characteristics, the proposed device has a high potential for future system-on-plastic integration. We believe that our research provide a novel choice for future low-cost embedded memory applications.