使用動態邊界與元件合併移除時序分析中共同路徑悲觀性之研究

Abstract

靜態時序分析(Static timing analysis)是現今IC設計中用來驗證時序收斂的一個關鍵步驟。然而，隨著快速成長的設計複雜度與晶片上的變異，靜態時序分析因而更加複雜。為了更精準地分析時序性能，共同路徑悲觀性移除(common path pessimism removal)是普遍用來修正在時脈路徑上透過時序分析產生的過度悲觀的結果。 為了避免窮舉電路中的所有路徑，在這篇論文裡，我們提出一種正確並快速的時序分析架構，採用以節點為基礎的靜態時序分析(block-based static timing analysis)，提出簡化時序圖、動態邊界和平行化運算。我們更進一步的延伸我們的演算法，可實際的用於半時脈週期路徑(half-cycle paths)、多時脈週期路徑(multi-cycle paths)跟時脈重聚(clock reconvergence)等三種情況的計算。實驗結果顯示我們提出的方法具高度的scalability，尤其是在大規模的電路中效果更加明顯。此外，我們提出的方法與TAU2014競賽前三名比較，達到正確的結果並且有超過2.13倍的加速效果。

Static timing analysis is a key process to guarantee timing closure for modern IC designs. Nevertheless, fast growing design complexities and increasing on-chip variations complicate this process. To capture more accurate timing performance of a design, common path pessimism removal is prevalent to eliminate artificially induced pessimism in clock paths during timing analysis. To avoid exhaustive exploration on all paths in a design, in this thesis, we present a novel timing analysis framework removing common path pessimism based on block-based static timing analysis, timing graph reduction, dynamic bounding, and parallel computing. We further introduce three practical extensions that are half-cycle paths, multi-cycle paths and clock reconvergence. Experimental results show that the proposed method is highly scalable, especially with short runtimes for large-scale designs. Moreover, our approach outperforms TAU 2014 timing contest winners, generating accurate results and achieving more than 2.13X speedups.