50Gb/s 115mW 全數位適應性決策回授等化器與雜訊抑制濾波器

Abstract

下一代的有線通訊系統对數據速率之要求達數十Gbps，故需要高速低功耗的等化器来補償高通道損失。適應性決策回授等化器 (ADFEs) 由於消除通道所造成之符號間彼此干擾（ISIs）現象並且能提高訊號雜訊比 (SNR）之優越的性能因而被廣泛使用。然而，因為適應性決策回授等化器在係數修正與資料等化處理上皆有回授路徑，會影響到實際所能處理的資料速度，導致適應性決策回授等化器在高速應用上受到一定的限制。因此，雜訊抑制連同擴展型的增量係數前瞻適應性決策回授等化器 (NS-EICL ADFEs）被提出來解決平行化所需要之架構。 NS-EICL ADFEs使用係數前瞻法接著配合適當的平行化來消除數據速率的限制以達到增加速度的目的。此外，配合該係數前瞻演算法，使用高通量的自前瞻濾波器和擴展濾波器(回授濾波器) 來實現硬體架構。連同緩慢更新率的批次模式係數更新單元(BMCU) 與雜訊抑制濾波器 (NSFs) ，無限數據速率和高輸出信噪比的等化器也能輕易的實現。然而，此概念要實現在高平行化的等化器，其回授模視所需的暫存器會隨著平行化而增長。因此，晶片面積和功耗也會隨著增加。 為了解決暫存器隨著平行化而增長，本論文提出了雙數據通路的自前瞻濾波器(DD-SLFs) 也就是自前瞻濾波器 (SLFs) 的修改版命名為雙路經 (Dual Data-paths) NS-EICL ADFE 。DD-SLFs的架構具有更好的能量效率和硬體面積，此因為 DD-SLFs在回授路段所需的暫存器比SLFs架構數量更少。此外，為了配合該DD-SLFs架構，此架構使用两组擴展濾波器來確定濾波器的初始數據。因此，與SLFs架構相比DD-SLFs沒有任何性能衰減。此外，gated clock技術再加上採用類似記憶體的架構取代暫存器的設計，也就是對很長的管線電路而言每次只會讀寫到兩個暫存器，因此可以大大降低整體功率消耗。為了達到濾波器最佳的能源效率，我們也提出了intelligent SNR-power management技能。此技能可于濾波器輸出信噪比来調整等化器的功耗，以達到最佳能源效率。 本論文將介紹兩顆不同架構的晶片，分別為四十倍平行的NS-EICL ADFE與五十倍平行的dual data-paths NS-EICL ADFE。實作上此兩片晶是採用40 nm CMOS-GP製程，操作在1 GHz系統時速。測量結果驗證，四十倍平行的NS-EICL ADFE能達到40 Gbps速率，擁有500 µm x 500 µm的片晶面積 (或約等效於292.5k個邏輯閘) ，個別功耗在-25 dB的通道當數據傳輸為40 Gbps 時分別為3.75 pJ/bit (0.87 V) ，48 Gbps，4.19 pJ/bit (0.9 V) 和58 Gbps，5.86 pJ/bit (1.04 V)。另一方面，根據post-layout模擬結果顯示，五十倍平行的dual data-paths NS-EICL ADFE能達到50 Gbps速率，連同intelligent SNR-power management (PM) 單元，晶片核心面積為653 µm x 653 µm (或約等效於345.81k個邏輯閘) ，操作在0.9 V與50 Gbps的速率，個別功耗分別為2.3 pJ/bit (-6 dB 通道) 和2.74 pJ/bit (-23.5 dB 通道) 。

Next generation wire-line communication system operate at multi-Gbps data rates becomes more demanding, the need for high-speed low power equalizers that can compensate on highly dispersive channels loss significantly increases. Adaptive Decision Feedback Equalizers (ADFEs) are widely used due to its superior performance to reduce the inter-symbol interferences (ISIs) caused by channels in communication systems and provide high signal-to-noise ratio (SNR). However, the data throughput rate of ADFEs is limited due to the feedback loops in the coefficients update part and data equalization part. Therefore, Noise-Suppression Extended Incremental Coefficients-Lookahead ADFEs (NS-EICL ADFEs) has been proposed. NS-EICL ADFEs uses the coefficients-lookahead scheme followed by parallelism to eliminate the limitation of data rate. Based on the coefficients-lookahead scheme, a high-throughput self-lookahead filter, and extended filter (feedback filter) are realized. Together with the slow update rate Batch Mode Coefficients Update (BMCU) unit and Noise-Suppression Filters (NSFs), an unlimited data rate and better output SNR ADFE is achieved. However, the number of delay elements grows quickly in the feedback loop with high parallelism of the ADFEs. Therefore, the hardware area and power are increased. In this dissertation, we propose a Dual Data-paths Self-Lookahead Filters (DD-SLFs) which is the modified version of previous SLFs design and is named (Dual Data-paths NS-EICL ADFE). DD-SLFs architecture have better energy efficiency and hardware area than SLFs architecture due to the number of delay elements in the feedback loop reduced. Based on the DD-SLFs architecture, two set of extended filters are used to determine the tentative decision data. Therefore, DD-SLFs have no performance degradation as is compared to SLFs architecture. Furthermore, gated clock technique with the design idea of register file architecture is used to replace pipelined delay elements to save power. Besides, in order to achieve an optimal energy efficiency ADFEs, an intelligent SNR-power management skill is proposed to optimize the overall power usages with required performance. Two test chips have been fabricated in 40 nm CMOS GP technology process and operates at 1 GHz system clock rate. The measurement result verify that with a 40 parallelism factor, 40 Gbps NS-EICL ADFE with core size 500 µm x 500 µm (or 292.5k equivalent gates count), and dissipates 3.75 pJ/bit at 40 Gbps with low-supply voltage (0.87 V), 4.19 pJ/bit at 48 Gbps with normal-supply voltage (0.9 V) and 5.86 pJ/bit at 58 Gbps with high-supply voltage (1.04 V) in -25 dB channel. On the other hand, with a 50 parallelism factor, dual data-paths architecture, and power management (PM) is taped out. The core size is 653 µm x 653 µm (or 345.81k equivalent gates count). It dissipates 2.3 pJ/bit at best channel (-6 dB) and 2.74 pJ/bit at worst channel (-23.5 dB) under 0.9 V supply voltage at 50 Gbps throughput rate, respectively.