24GHz低功率高增益接收端架構設計與分析

Abstract

本論文討論分為兩部分，其中所提出電路之晶片製作皆由TSMC 0.18 μm mixed-signal/RF CMOS 1P6M製程來實現。 第一部分為一個在k-band的三級寬頻低雜訊放大器。這個低雜訊放大器設計使用了兩級的共源級及串疊了一個共源級共閘級。模擬的結果顯示了這個電路為低雜訊及低功率同時還保有高增益的優點。然而，在量測的過程中，有部分頻段會震盪，調整整體電路的偏壓過後，量測的結果不像模擬的結果如此的漂亮。根據量測結果，3-dB頻寬是3GHz，從23 – 26GHz，增益最大值在21GHz為8dB。在23 – 26GHz的頻率範圍中，放大器的輸入及輸出端反射係數皆小於 -10dB，而雜訊指數則為5.5 - 6.8dB。在24GHz時，其三階截斷點為 -10dBm，1 dB 增益壓縮點為-7dBm。整體的功率耗損是23.4mW，量測結果的FOM為0.227。 第二部分提出了一個使用交感耦合的高增益降頻混波器。在這個設計中，第一級的設計為差模輸入的低雜訊放大器搭配交感耦合，轉導級使用了電流注入的方式，使的整體的電路同時擁有高增益和低功率。但由於後模擬的過程中沒有模擬的十分周行，導致這顆電路會在中頻的訊號附近震盪。在這顆混頻器的模擬結果中，其增益高達19.53dB，而3dB頻寬為9GHz，雜訊指數最小值為7.5dB。在24GHz時，其三階截斷點為 -9dBm，1 dB 增益壓縮點為-13.7dBm。整體電路(不包含輸出的緩衝器)的功率消耗為4.79mW。 第三部分提出了一個24GHz高增益低功率的前端接收機。在這一章節中使用了一個新提出的低雜訊放大器、一個巴倫和使用了上個章節所用的混頻器。結果顯示出此接收端的轉換增益為31dB，雜訊指數為5.45dB。在24GHz時三階截斷點為 -11dBm，1dB增益壓縮點為-25dBm。在隔離度的部分，LO - IF的隔離度小於-50dB，LO – RF的隔離度小於-50dB，RF-IF的隔離度小於-35dB。整體的功率消耗(不包含輸出緩衝端)為24.59mW。

This thesis consists of three parts. All the proposed circuit were implemented in TSMC 0.18μm mixed-signal/RF CMOS 1P6M technology. Part I present a three-stage wideband LNA design in k-band. This LNA design use two-stage common-source and one-stage cascode structure. The simulation result shows the noise and power of the proposed circuit is low while the gain is high. The measurement result, however, is not as good as the simulation result owing to the oscillation occurring on certain frequency. According to the 3-dB bandwidth is 23 – 26 GHz and the peak gain is 8 dB at 21 GHz. The input return loss and output return loss are below -10 dB. The noise figure is 5.5 – 6.8 over the frequency band. The P1dB is -7dBm and IIP3 is -1.15 dBm at 24GHz. Total power dissipation is 23.4mW. The measured FOM of the proposed LNA is 0.227. Part II proposed a high gain down-conversion mixer with capacitance cross-coupled technique. The first stage of the proposed design is a differential LNA with cross-coupled design; the switching stage uses the current bleeding technique; these ensure high gain and low power dissipation. Due to the imperfect post-simulation, the measurement oscillates at the IF frequency. The simulated gain of the mixer reaches 19.53 dB and the 3-dB BW is 9GHz; the double-side band minimum noise figure is 7.5 dB; the P1dB is -13.7 dBm and the IIP3 is -9dBm at 24GHz. The power dissipation excludes the output buffer is 4.79mW. Part III presents a 24GHz high gain low power receiver front-end. In this chapter a new LNA and balun is implemented and the mixer is reused in last chapter. The conversion gain is 31dB and the noise figure is 5.45 dB; IIP3 is -11 dBm and the P1dB is -25 dBm at 24GHz. The LO-IF leakage is less than -50 dB; the LO-RF leakage is less than -50dB; the RF-IF leakage is less than -35dB. Total power consumption excluded output buffer is 24.59 mW.