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dc.contributor.authorLin, Horng-Chihen_US
dc.contributor.authorHung, Cheng-Hsiungen_US
dc.contributor.authorChen, Wei-Chenen_US
dc.contributor.authorLin, Zer-Mingen_US
dc.contributor.authorHsu, Hsing-Huien_US
dc.contributor.authorHunag, Tiao-Yuangen_US
dc.date.accessioned2014-12-08T15:09:56Z-
dc.date.available2014-12-08T15:09:56Z-
dc.date.issued2009-03-01en_US
dc.identifier.issn0021-8979en_US
dc.identifier.urihttp://dx.doi.org/10.1063/1.3086271en_US
dc.identifier.urihttp://hdl.handle.net/11536/7585-
dc.description.abstractIn this work we report the observation and characterization of a hysteresis phenomenon in the transfer characteristics of n-channel polycrystalline silicon (poly-Si) thin-film transistors (TFTs). Such phenomenon is observed in devices with fully depleted channel and not treated with hydrogen-related anneal. The origin of the hysteresis is identified to be related to the electron trapping and detrapping processes associated with the deep-level traps in the grain boundaries of the poly-Si channel.en_US
dc.language.isoen_USen_US
dc.subjectdeep levelsen_US
dc.subjectdefect statesen_US
dc.subjectelectron trapsen_US
dc.subjectelemental semiconductorsen_US
dc.subjectgrain boundariesen_US
dc.subjecthysteresisen_US
dc.subjectinterface statesen_US
dc.subjectsiliconen_US
dc.subjectthin film transistorsen_US
dc.titleOrigin of hysteresis in current-voltage characteristics of polycrystalline silicon thin-film transistorsen_US
dc.typeArticleen_US
dc.identifier.doi10.1063/1.3086271en_US
dc.identifier.journalJOURNAL OF APPLIED PHYSICSen_US
dc.citation.volume105en_US
dc.citation.issue5en_US
dc.citation.epageen_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000264156300101-
dc.citation.woscount6-
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