Origin of hysteresis in current-voltage characteristics of polycrystalline silicon thin-film transistors

標題:	Origin of hysteresis in current-voltage characteristics of polycrystalline silicon thin-film transistors
作者:	Lin, Horng-Chih Hung, Cheng-Hsiung Chen, Wei-Chen Lin, Zer-Ming Hsu, Hsing-Hui Hunag, Tiao-Yuang 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics
關鍵字:	deep levels;defect states;electron traps;elemental semiconductors;grain boundaries;hysteresis;interface states;silicon;thin film transistors
公開日期:	1-三月-2009
摘要:	In this work we report the observation and characterization of a hysteresis phenomenon in the transfer characteristics of n-channel polycrystalline silicon (poly-Si) thin-film transistors (TFTs). Such phenomenon is observed in devices with fully depleted channel and not treated with hydrogen-related anneal. The origin of the hysteresis is identified to be related to the electron trapping and detrapping processes associated with the deep-level traps in the grain boundaries of the poly-Si channel.
URI:	http://dx.doi.org/10.1063/1.3086271 http://hdl.handle.net/11536/7585
ISSN:	0021-8979
DOI:	10.1063/1.3086271
期刊:	JOURNAL OF APPLIED PHYSICS
Volume:	105
Issue:	5
結束頁:
顯示於類別：	期刊論文

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