TNAPL:三維積體電路針對矽穿孔雜訊改良的佈局擺置

Abstract

本篇論文提出了一個力導向的廣域平面布局擺置，針對三維積體電路中矽穿孔結構彼此間的雜訊干擾作改良，試圖在擺置時在矽穿孔之間施予一排斥力將耦合較強的矽穿孔拉開以降低其雜訊的干擾，而排斥力的大小是由矽穿孔彼此間的雜訊轉換而來，藉此降低所有矽穿孔彼此間的雜訊影響。在所有實驗中，反耦合排斥力有效的將雜訊平均降低36.8%並只增加7.4%的繞線長度。此外，本論文提出的三維積體電路廣域布局擺置在繞線長度上表現也十分優異，可以和現今其他的研究做比較。

In this work, we proposed a force-directed global placement method to optimize the coupling noise between TSVs in 3D ICs. We introduce a decoupling force to separate the TSVs with strong coupling to reduce the noise, and the force magnitude is determined by the coupling noise, then we are trying to reduce the total TSV noise. In all experiments, the decoupling force reduce the total noise effectively for 36.8% in average and cause only 7.4% wirelength overhead. Besides, the 3D placement we proposed shows great performance in wirelength which is competitive to state-of-art 3D placer.