NaDaP:三維積體電路針對矽穿孔雜訊及分佈密度改良的佈局擺置

Abstract

本篇論文提出了一個以力導向為基礎的三維積體電路中矽穿孔雜訊及密度改善的 廣域平面佈局擺置，進而改善矽穿孔結構彼此間總雜訊干擾及最大峰值雜訊干 擾，峰值雜訊干擾將會導致數位積體電路設計時的功能錯誤，而最大雜訊的值和 矽穿孔在晶片中的分佈相關。在先前的實驗中，雜訊排斥力用來降低雜訊的總量， 而初略合法化力用來改善元件的重疊性，再者，我們引進了矽穿孔密度力來改善 矽穿孔的分佈密度，密度力的主要想法是將位於高密度區域的矽穿孔移動至低密 度區域，在所有實驗中，應用矽穿孔雜訊排斥力結合密度力擺置的表現相較於針 對線長的擺置，平均來說有效地降低42.6%的最大雜訊和15.0%的總雜訊，並只增 加4.6%的繞線長度。相較於只結合矽穿孔雜訊排斥力的擺置，總雜訊和最大峰值 雜訊分別降低4.4%和26.4%，線長也縮短了0.9%。

In this work, we proposed a TSV noise-aware & density-aware technique based on force-directed placement to reduce total noise and maximum peak noise of TSV in 3-D IC global placement stage. The peak noise value, which may lead to function errors in digital circuit design is relative to the TSV distribution in die area. In previous works, the decoupling forces are used to reduce the total noise of TSVs, and the rough legalize forces are used to improve the cell overlap. Then, we introduce the density force to adjust the TSV density. The main idea of TSV density force is trying to push the TSVs in high density bin to low density bin. In all experiments, the TSV coupling force combine with TSV density force effectively reduces the maximum peak noise for 42.6% and the total noise for 15.0% in average and causes only 4.6% wirelength overhead compared to wirelengh-driven placement, moreover, compares with the result of decoupling forces only placement, the total noise and the maximum peak noise are 4.4% and 26.4% smaller respectively, and the wirlength is 0.9% shorter.