新穎性奈米尺度多重閘極無接面電晶體之研究

Abstract

本篇論文中，我們將使用三維量子修正元件模擬無接面梯形通道和鰭式場效電晶體(FinFET)分別建立在單晶矽基板和絕緣體覆矽(Silicon-on-insulator, SOI)的電特性比較。研究元件電性包括次臨界擺幅(Subthreshold slope, SS)、汲極引致能障下降(Drain-induced barrier lowering, DIBL), 漏電流(Off-current, Ioff)及臨界電壓(Threshold voltage, VTH) 的滾降，並且會研究隨著不同角度和鰭式通道產生的變化。無接面鰭式場效電晶體使用單晶矽基板技術展現較優異的短通道特性(Short channel characteristics)，對於梯形通道的閘極控制能力(Gate controllability)和對於鰭式通道角度變化較不為敏感的電特性，這是因為基板與通道產生的接面以致於等效通道厚度減少所造成。因此強烈建議在10奈米以下製程採用單晶矽基板製成無接面鰭式場效電晶體。 此外本篇論文首次開發製成混合式P/N有著omega狀閘極和奈米線(Nanowires)結構之多晶矽無接面薄膜電晶體(Junctionless thin-film transistor, JL-TFT)。此新穎的元件展現了極佳的電特性，像是超陡峭之次臨界擺幅(Subthreshold swing, SS) 64mV/dec、較高的開關電流比(Ion/Ioff current ratio) >107、較低的汲極引致能障下降(Drain-induced barrier lowering, DIBL)值為3mV/V和小串聯電阻(Series resistance, Rs)，此外本結構對I-V特性對溫度有優異安定性也加以探討，也量子效應及晶體振動模型于以初步的闡述。但更深入的探討還須更進一步研究。論文將指出此新穎元件因為相較於傳統無接面薄膜電晶體有較好的閘極控制能力和較少的擁擠電流(Current crowding)。此外，模擬結果與實驗數據相符。因此提出此混合式P/N無接面薄膜電晶體將非常有希望助為未來元件微縮和三維堆疊積體電路之應用。

In this thesis, we presented electrical characteristics of trapezoidal shaped channel for the junctionless (JL) bulk and silicon-on-insulator (SOI) FinFET are numerically explored by using 3D quantum-corrected device simulation. The dependence of device performances, including subthreshold slope, drain-induced barrier lowering, off-current and threshold voltage roll-off, on the various fin angle and fin height are investigated. The JL bulk FinFET exhibits excellent short channel characteristics, gate controllability over trapezoidal shaped channel and less sensitivity of the fin angle to electrical performances by reducing effective channel thickness that is caused by the channel/ substrate junction. Hence, the JL bulk FinFET is highly recommended in sub-10-nm nodes. Additionally, this work demonstrates for the first time the fabrication of a proposed hybrid P/N poly-Si channel junctionless thin-film transistor (JL-TFT) with nanowires and omega-gate structure. The novel hybrid P/N JL-TFTs showed excellent electrical performances in terms of a steep subthreshold swing of 64mV/dec, a high Ion/Ioff current ratio (>107), a low drain-induced barrier lowering value of 3 mV/V, small series resistance and temperature stability were investigated, indicating greater gate electrostatic controllability and less current crowding than in conventional JL-TFTs. Furthermore, simulated results and a quantum model physical model were discussed initially but not detailed enough for future work support experimental data. Hence, the proposed hybrid P/N JL-TFT is highly promising for future further sub-10-nm scaling and 3D stacked ICs applications.