利用四值編碼考慮訊號轉換效應的邏輯功能時序分析

Abstract

現在電路的時序分析致力於計算出準確且實際的臨界路徑延遲。邏輯功能時序分析(functional timing analysis)消除了錯誤路徑所以提供了比起傳統靜態時序分析(static timing analysis)更好的時序收斂(timing closure)。但是之前的邏輯功能時序分析並未考慮到訊號轉換產生的效應，像是多輸入轉換(multiple inputs switching)、耦合(coupling)。多輸入轉換改變邏輯閘的引腳延遲(pin-to-pin delay) 進而改變電路的延遲時間，所以我們提出了一個利用四值編碼考慮訊號轉換的邏輯功能時序分析稱之為TA-FTA，TA-FTA可以消除錯誤路徑同時考慮到訊號轉換效應如同其命名。然而，當我們考慮了訊號轉換效應，時序分析的過程變得十分複雜繁瑣。因此我們同時提出了兩個方法加速TA-FTA。之後我們把TA-FTA應用在多輸入轉換效應，實驗結果顯示，TA-FTA計算出一個比起傳統的時序分析延遲多38%的結果，證明訊號轉換效應是不可忽視的。並且我們也實驗我們提出的加速方法的顯示有使用此兩種方法可以比起不使用達到百倍以上的加速效果。

To calculate an accurate and practical path delay becomes a profound issue for timing analysis of modern circuit designs. The emerging functional timing analysis (FTA) eliminates false paths and provides better timing closure than static timing analysis (STA) does. However, all previous FTA works have not yet considered signal transitions. The signal-transition effect, such as multiple inputs switching (MIS), changes the pin-to-pin delay of a gate and thereby increases overall circuit delay. As a result, we propose a transition-aware FTA framework named TA-FTA using a novel four-valued encoding for calculating true delay subject to signal transitions. However, once we consider signal transition effect, timing analysis becomes sophisticated. Therefore, we also propose two methods to speed up TA-FTA. Furthermore, we apply TA-FTA to analyze the MIS effect. Experimental results show that for the worst case of all benchmark circuits, the circuit delay derived by TA-FTA increases by 38% of that calculated by traditional FTA. Experimental results also shows that execution time with our two speed-up techniques is faster more than hundreds times compared to those without two techniques.