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dc.contributor.authorKuo, Po-Yien_US
dc.contributor.authorChao, Tien-Shengen_US
dc.contributor.authorLai, Jiou-Tengen_US
dc.contributor.authorLei, Tan-Fuen_US
dc.date.accessioned2014-12-08T15:09:57Z-
dc.date.available2014-12-08T15:09:57Z-
dc.date.issued2009-03-01en_US
dc.identifier.issn0741-3106en_US
dc.identifier.urihttp://dx.doi.org/10.1109/LED.2008.2011146en_US
dc.identifier.urihttp://hdl.handle.net/11536/7602-
dc.description.abstractWe have successfully developed and fabricated the vertical n-channel polycrystalline silicon thin-film transistors with symmetric S/D fabricated by Ni-silicide-induced lateral-crystallization technology (NSILC-VTFTs). The NSILC-VTFTs are S/D symmetric devices and equivalent to dual-gate devices. The dualgate structure of NSILC-VTFTs can moderate the lateral electrical field in the drain depletion region, significantly reducing the leakage current. In NSILC-VTFTs, the Ni accumulation and grain boundaries induced from S/D sides can be centralized in the n(+) floating region. The. effects of Ni accumulation in symmetric VTFTs crystallized by NSILC and metal-induced lateral crystallization are studied. In addition, a two-step lateral crystallization has been introduced to improve the crystal integrity through secondary crystallization. The NSILC-VTFTs crystallized by two-step lateral crystallization show a steep subthreshold swing of 180 mV/dec and field effect mobility mu = 553 cm(2)/V . s without NH(3) plasma treatment.en_US
dc.language.isoen_USen_US
dc.subjectDual gateen_US
dc.subjectn(+) floating regionen_US
dc.subjectNi-silicide-induced lateral crystallization (NSILC)en_US
dc.subjectpolycrystalline silicon thin-film transistors (poly-Si TFTs)en_US
dc.subjectsymmetric S/Den_US
dc.subjectvertical channelen_US
dc.titleVertical n-Channel Poly-Si Thin-Film Transistors With Symmetric S/D Fabricated by Ni-Silicide-Induced Lateral-Crystallization Technologyen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/LED.2008.2011146en_US
dc.identifier.journalIEEE ELECTRON DEVICE LETTERSen_US
dc.citation.volume30en_US
dc.citation.issue3en_US
dc.citation.spage237en_US
dc.citation.epage239en_US
dc.contributor.department電子物理學系zh_TW
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electrophysicsen_US
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000263920400012-
dc.citation.woscount2-
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