使用具校正機制時間放大器之時間數位轉換器之全數位鎖相迴路

Abstract

近年來通訊3C產品以急快的速度發展，相關3C產品的更新速度已非同日而語。無線通訊IC中不管是發射器(Transmitter)或接收器(Receiver)，乃至於類比數位轉換電路，都需要使用鎖相迴路來產生一乾淨的時脈。做為電路的核心部分，鎖相迴路是相當重要的時脈產生電路。類比鎖相迴路已經有數十年的發展歷史，但是近年來為了能配合製程微縮以及降低晶片面積成本等考量下，全數位鎖相迴路漸漸成為主流。類比鎖相迴路的缺點是只要製程更換就必須重新設計，且濾波器中的電阻電容無法隨製程微縮；而全數位鎖相迴路皆以數位邏輯電路構成，在製程微縮上具有相當的優勢，因此現今研究主流為全數位鎖相迴路，以期改善類比鎖相迴路無法直接微縮的缺點。相對全數位鎖相迴路在時間抖動量的效能並無法完全追上類比鎖相迴路，因此還需要投入更多心力研究如何接近類比鎖相迴路的效能表現。 在本篇論文中，以全客戶式設計實現全數位鎖相迴路，並設計一個具校正機制的時間放大器，讓時間放大器正常放大兩倍的範圍能夠增加，並將此具校正機制時間放大器運用在時間數位轉換器，藉此提高時間數位轉換器的解析度，以降低全數位鎖相迴路的時間抖動量。全數位鎖相迴路的輸出頻率為2.4GHz。 晶片量測結果顯示輸出頻率正確鎖定在2.4GHz；峰對峰時間抖動量(Peak to Peak jitter)的量測結果為26.67ps，RMS jitter為3.38ps，功率消耗為16.76mW，晶片核心面積為0.27 。

In recent years, the 3C products (Computer, Communication and Consumer electronics) have developed extraordinarily quickly. For wireless communication ICs, in either the transmitter or receiver, they all need a phase-locked loop (PLL) circuit to supply a clean clock source, so the phase-locked loop which is the core of the circuit is a very important clock generator. The analog phase-locked loop (APLL) has been developing for several years. However, in recent years, the all-digital phase-locked loop (ADPLL) has gradually become the mainstream in process scaling and small chip area. The drawback of the analog phase-locked loop is that it must be redesigned with process scaling down and the size of resistor and capacitor in the filter cannot be scaled down with the process, while the ADPLL is consisted of the digital logic circuits which can be scaled down directly. The ADPLL improves the analog phase-locked loop to process scaling down directly. However, the performance of ADPLL is usually not as good as the APLL, so it is necessary to put more efforts on how to improve the jitter performance of the ADPLL. In this thesis, we implement the ADPLL by using full-custom design flow. We design a calibration mechanism for the time amplifier which can increase the amplification range of the time amplifier. This time amplifier with the calibration mechanism is used in the time to digital converter (TDC), and improves the resolution of the TDC to reduce the jitter of the ADPLL. The output frequency of ADPLL is designed as 2.4GHz. From the measurement result, the output frequency of the ADPLL can be locked at 2.4GHz, the amount of the peak-to-peak jitter is 26.67 ps, and the RMS jitter is 3.38ps. The power consumption of this chip is 16.76mW. The core area of the chip is 0.27 .