低溫晶圓接合研究及其三維堆疊整合應用

Abstract

本論文針對低溫晶圓堆疊接合技術進行研究開發，並提出兩種創新架構與方法，分別供記憶體堆疊及影像感測器模組應用。其一為低溫微凸塊與接合膠材混合式晶圓接合技術與創新架構，可提供微間距高密度連接需求之低溫接合記憶體堆疊。另一為低溫接合膠材搭配晶圓處置之暫時性接合與移除技術，提出創新架構與製程方法供下世代影像感測器晶圓級封裝應用。本論文鎖定250°C以下低溫晶圓接合為研發標的，以降低晶圓接合過程中衍生之結構熱應力與可能損壞風險，滿足多數元件低熱預算需求。 在記憶體堆疊應用部分，本論文首先利用銅矽穿孔搭配微凸塊與接合膠材混合式接合，完成晶圓級三維堆疊整合架構與方法，將可簡化製程步驟與提升產出率，提供一低成本、低溫、高可靠度之解決方案；其中利用銅/錫微凸塊與高分子接合膠材進行低溫混合式接合，可同時達到銅/錫金屬本質上之電訊連接，以及堆疊接合晶圓間之微間隙膠材填充與密封效果，不但能保護電訊連接接點，提升堆疊元件可靠度，並可增加晶圓接合之機械強度，以及耐受接合後之晶圓薄化與一連串之晶背製程，此創新堆疊接合架構因此不需額外之carrier使用，並能省去傳統晶片堆疊組裝之微間隙underfill填充與flux清潔等製程與困難挑戰，因此能大幅簡化步驟、提升良率、降低成本。首先，數種半導體相容且常用之介電保護材料被挑選進行作為混接膠材評估，其本身接合效能，以及與金屬搭配進行混合式接合之相容性，均進行測試評估；並針對幾個影響混合式接合之重要因子進行研究，進而找出最佳化銅/錫與相容膠材之混接條件以優化接合品質。藉由金屬凸塊與接合膠材厚度搭配之精準控制，以及有效潔淨化接合金屬表面狀態，透過採用銅/錫凸塊與圖案化BCB接合膠材搭配之混合式接合技術，將可有效應用於三維堆疊整合。 決定混合式接合搭配材料後，本論文進一步研發利用銅矽穿孔搭配銅/錫微凸塊與BCB接合膠材混接之晶圓級三維整合創新架構與方法，並設計研究不同矽穿孔/凸塊尺寸與間距組合之測試載具晶圓，其中包括daisy chain、Kelvin structure及TSV leakage測試圖案設計，以進行特性分析研究；關鍵技術包括矽穿孔製作、微凸塊製作、混接結構成形、混合式接合、晶圓薄化及晶背金屬化製作等，透過進行製程模組開發與整合來實現此三維整合創新架構；藉由這些關鍵技術之有效研發與整合，本論文成功開發整合了5µm矽穿孔、10µm微凸塊、20µm細間距、40µm薄晶圓及250°C低溫晶圓混接技術於此三維整合架構平台上。 接續此銅矽穿孔搭配銅/錫微凸塊與BCB接合膠材混接之晶圓級三維整合創新架構成功開發，5μm與10μm矽穿孔組合之daisy chain與Kelvin structure測試晶圓被進一步製備，以進行此三維接合結構之電特性與可靠度研究分析；此外，具測試圖案之成對矽穿孔也被設計製作，以研究兩根矽穿孔間之漏電流。微接點、單一銅矽穿孔與銅/錫微凸塊連接、以及一連串銅矽穿孔與銅/錫微凸塊之接合連接鍊結構等特性分析結果，顯示此三維接合創新架構具有極佳之電性表現，並能通過包括交流電應力循環測試、溼度測試及熱循環測試等可靠度測試評估。所有分析評估結果皆顯示此三維整合創新架構具有極佳的電性表現與可靠度，未來將可廣泛於記憶體堆疊等三維堆疊產品應用。 除上述適用於記憶體堆疊之三維整合創新架構外，本論文另針對下世代背照射影像感測晶圓封裝模組技術，提出一利用低溫接合膠材搭配晶圓暫接處置與移除技術之新式晶圓封裝架構與製程方法。首先設計測試載具晶圓，以進行此新式背照射影像感測晶圓封裝結構與製程之測試開發與整合。有別於傳統封裝技藝，此創新架構與方法不需額外carrier晶圓使用於封裝結構中(暫接處置用carrier可回收重複利用)，並可省去要求嚴格且複雜之晶圓融合接合(fusion bonding)與矽穿孔製程，因此同樣具有大幅簡化步驟、提升良率與降低成本之優勢。特性分析與可靠度測試結果亦顯示此新式整合封裝架構具有極佳之整合縮裝效能、電性表現與可靠度。接著，進一步設計製作功能性晶圓以進行功能測試驗證，本論文成功研發展示了背照射影像感測器與類比數位轉換器之堆疊整合，並通過了具良好成像品質之影像功能測試。此新式三維整合封裝架構提供了一個可實行的低成本解決方案，可提供下世代影像感測器與未來三維整合影像感測器應用。

In this thesis, novel schemes using low-temperature wafer bonding technology for memory stacking and CMOS imager sensor (CIS) module applications are developed and investigated. One is low-temperature micro-bump and adhesive hybrid wafer bonding with fine pitch interconnect for memory stacking. The other is novel scheme with low-temperature adhesive bonding combination with temporary bonding/de-bonding technique for CIS wafer-level packaging (WLP). The low-temperature wafer bonding technologies are targeted to be less than 250 °C, which decreases the induced thermo-stress and possible damages, and satisfies low thermal budget requirement on most devices. A wafer-level 3D integration scheme with Cu TSVs based on micro-bump and adhesive hybrid bonding is developed to provide a simplified flow, low temperature, and highly reliable solution for memory stacking. Herein Cu/Sn micro-bump and polymer adhesive are adopted for low temperature hybrid bonding to achieve intrinsic interconnect with adhesive sealing around. This scheme also enhances the reliability of the stacked devices and serving as reinforcement of the mechanical stability to withstand the severe wafer thinning and backside processes. Firstly, several popular passivation materials are evaluated as the hybrid bonding adhesive. The bonding integrity and hybrid compatibility with metal of these materials are investigated and assessed. Some key factors for hybrid bonding are studied, and the conditions of Cu/Sn and qualified adhesive hybrid bonding are optimized to enhance the bonding performance. With precise control of metal/adhesive thickness and clean metal surface, the hybrid scheme of Cu/Sn bump and patterned Benzocyclobutene (BCB) adhesive is qualified and can be adopted to perform 3D integration. Accordingly, a wafer-level 3D integration scheme with Cu TSVs based on Cu/Sn micro-bump and BCB adhesive hybrid bonding is further developed and demonstrated. TEG wafer with different TSV/bump sizes and pitches are designed with daisy chain, Kelvin structure, and TSV leakage test patterns for investigation and characterization. Key technologies, including TSV fabrication, micro-bumping, hybrid scheme formation, hybrid bonding, wafer thinning, and backside RDL formation are developed and integrated to perform the 3D integration scheme. 40-µm thickness wafers with 5 µm TSVs, 10 µm micro-bumps with 20 µm pitch, using 250 °C low temperature W2W hybrid bonding are successfully integrated in the 3D integration platform. Following the successful development of the wafer-level 3D integration scheme with Cu TSVs based on Cu/Sn micro-bump and BCB adhesive hybrid bonding, daisy chain feature and Kelvin structure with 5 μm and 10 μm TSV in the scheme are fabricated and investigated with electrical characterization and reliability assessment. TSV pair with test pattern is designed for the leakage investigation. The characteristics of micro-joint, single Cu TSV, and Cu/Sn micro-joint interconnect, and bond chain structure with a series of Cu TSVs and Cu/Sn micro-joints interconnect are investigated with excellent performance, and the scheme can pass multiple AC current stressing, humidity test, and TCT reliability assessment. The characterization and reliability assessment results indicate that the 3D integration scheme possesses excellent electrical performance and reliability, and could be extensively applied for 3D product applications. In addition, another novel scheme with low-temperature adhesive bonding combination by utilizing temporary bonding/de-bonding technique for backside illuminated (BSI) CIS wafer-level packaging is investigated and developed. TEG wafer is designed first to evaluate and integrate the novel BSI-CIS structure and process, where no carrier wafer is required and the complex fusion bonding and TSV fabrication processes can be skipped accordingly. The characteristics and reliability of the scheme are investigated, results show excellent integration integrity and reliability. Real device wafer is then designed for further verification and demonstration with functional test. Stacking of BSI-CIS and analog-to-digital converter (ADC) real device is demonstrated. The image function is successfully verified with good quality, which indicates the excellent performance as well. This scheme provides a realizable low cost solution for the next generation CIS and further 3D integrated imager applications.