高效能銦鋅錫氧化物薄膜電晶體元件開發與研究

Abstract

近年來透明非晶態金屬氧化物半導體為目前最具發展潛力的薄膜電晶體主動層材料，尤其是銦鎵鋅氧化物半導體，兼具非晶矽材料的高均勻性以及低溫多晶矽(Poly-Si)材料的高載子遷移率之優點，並擁有低溫成長以及高可見光穿透率等物理特性，因此極有機會取代非晶矽與多晶矽成為下世代的薄膜電晶體材料。然而隨著未來顯示器的應用如立體顯示器、有機發光顯示器、大尺寸高解析度的面板以及整合周邊驅動電路的應用，銦鎵鋅氧化物半導體已漸漸不敷使用。是故本論文著重於開發新穎式高效能非晶態氧化銦鋅錫半導體材料並深入研究其材料基本光電特性，此新式氧化物半導體相較於銦鎵鋅氧化物半導體之優勢為： (1) 薄膜不含貴重及稀土元素“鎵”，因此成本較低，同時鋅以及錫都是地球中含量豐富的金屬，以長久的發展性而言，具有較高的潛力；(2) 具有較高載子濃度以及導帶由相似半徑的金屬s軌域所構成，因此載子在薄膜內的傳遞行為較佳；(3) 由於加入了氧化錫於材料中，薄膜對於酸鹼容液具有較高的抗蝕刻力，因此將更有機會製作背通道蝕刻型結構之薄膜電晶體元件，對於節省成本以及微縮元件具有相當大的優勢。在本研究中，我們成功開發透明非晶態氧化銦鋅錫半導體材料並將應用於薄膜電晶體元件，作為元件通道層。 本論文首先探討不同氧含量於氧化銦鋅錫薄膜中對於元件電特性的影響，發現在濺鍍沉積薄膜時通入適當的氧氣將有助於修補薄膜內因氧空缺而形成的淺層缺陷能態，改善基本電特性以及元件操作可靠度，同時我們再藉由不同的可靠度量測與分析，探討氧含量與能隙間缺陷能態的分佈與影響。再來我們也探討後續處理技術(爐管退火)改善氧化銦鋅錫薄膜電晶體元件電特性並探討其改善機制，其中發現隨著退火溫度的提升，在不影響薄膜結構的情況下，薄膜內的缺陷密度或是介面缺陷密度將能有效地減少因而改善元件次臨界擺幅和載子遷移率，同時元件的電壓操作可靠度也能大幅改善，透過簡單的參數萃取以及模型計算，能有效地將改善效果量化出來。最後本論文將研究元件保護層對於氧化銦鋅錫薄膜電晶體元件的影響，探討不同的沉積方式:電漿輔助式化學氣相沉積以及原子層沉積，沉積二氧化矽以及氧化鋁薄膜於元件作為保護層，透過調整不同製程前驅物並搭配正壓氧氣退火來進一步優化元件特性，藉由材料特性分析的佐證來說明元件電特性上的變化。我們發現以具有較低電漿轟擊的沉積方式: 電漿增強式原子層沉積法沉積之氧化鋁作為保護層的元件具有較好的電特性表現以及較高的穩定性，其最佳化的元件具有30.16 cm2/Vs的載子遷移率，-0.88 V的臨界電壓(Vth)以及0.34 V/decade的次臨界擺幅。

In recent years, the transparent amorphous oxide semiconductor (TAOS) has attracted a lot of attention to replace the silicon material as the channel layer of thin film transistors (TFTs). Among these materials, the indium gallium zinc oxide (InGaZnO: IGZO) semiconductor is most popular and considered to be the promising candidates for array technology owing to the characteristics of transparent, high mobility, good uniformity, low-temperature deposition which are superior than both polycrystalline silicon and amorphous silicon. However, the average field-effect mobility of a-IGZO TFTs is not high enough (≧30 cm2/Vs) for future display applications such as ultra-high definition (UHD) display, active matrix organic light-emitting diode displays (AMOLEDs) and system driving circuits integrated with the TFT array process. In this dissertation, the transparent amorphous indium zinc tin oxide (InZnSnO: IZTO) has been developed for achieving high mobility TFTs, where the optical and electrical characteristics of this material are also well discussed. Compare with IGZO, a cheaper TAOS material can be obtained in IZTO due to the replacement of the rare element: gallium to the tin metal which is plenty in the earth cruer. The structure disorder issue in multi-cation oxide semiconductor in the conduction band can be mitigated due to the similar size of unoccupied s-orbital (4d105s0) in In3+ ion and Sn4+ ion which leading the better electron conducting behavior. Moreover, the etch resistance of IZTO layer against chemical etchants can be enhanced due to the incorporation of tin oxide which realizes the back-channel-etch (BCE) structure for oxide TFTs. In this study, we have successfully developed transparent amorphous IZTO semiconductor and applied it as the channel layer material for fabricating IZTO TFTs. First, the electrical performance of a-IZTO TFTs with various oxygen incorporations has been investigated in this work. With suitable oxygen flow rate during sputtering, i.e., 0.1 sccm, the defect states near the conduction band minimum (CBM) could be eliminated with superior electrical performance of a-IZTO TFTs. The relation between oxygen incorporation and amount of oxygen-vacancy-related defects distributed in the mid-gap of IZTO channel can also be qualitatively analyzed. The post-thermal-annealing effect for the high carrier mobility a-IZTO TFT device was also well discussed in this work. The annealing process provides the thermal energy for structure relaxation of a-IZTO thin film, which obviously reduces both defect states in the a-IZTO channel and at the a-IZTO/SiO2 interface. The defect elimination during thermal annealing process can be quantified by the numerical calculation extracted from the sub-threshold swing (s.s.) and fitting the threshold voltage (Vth) shift with stretched-exponential model during bias stress reliability test. In the last of this study, the effect of passivation layer on electrical performance of a-IZTO TFTs was investigated. The SiO2 and Al2O3 deposited by PECVD and ALD, respectively, were adopted as the passivation layer for devices. The optimized performance of passivated a-IZTO TFTs can be obtained by adjusting the reacted precursor or gas flowing rate during passivation layer deposition. Then, the high pressure annealing was also adopted for further improvement. The a-IZTO TFTs with Al2O3 passivation layer deposited by plasma-damage-free ALD perform a superior electrical transfer characteristic with mobility of 30.16 cm2/Vs, (Vth) of -0.88 V and s.s. of 0.34 V/decade and highly stable reliability results.