應用高介電常數絕緣層與矽奈米微晶粒於超大型積體電路元件之研究

Abstract

本論文首先對於高介電常數鈷鈦酸(CoTiO3)絕緣層穩定性的改善，提出三種摻雜氮的方法。利用氮氣分子(N2+)或原子(N+)離子，以低能量植入鈷鈦金屬堆疊之中，接著進行氧化，利用電子顯微鏡與X光繞射(X-Ray Diffraction)方法均觀察到結晶狀態被氮摻雜抑制，電性量測亦證明了可以降低漏電，提高崩潰電壓，並在電壓加壓下有較佳穩定性。或利用一氧化二氮(N2O)之電漿進行氮摻雜，先以較低的氧化溫度形成鈷鈦酸氧化物，接著進行一氧化二氮電漿處理，之後再經一道高溫熱退火步驟。我們發現以此方法可以有效改善鈷鈦酸絕緣層的熱穩定性，同時提升絕緣層的電性可靠度，絕緣層漏電可以降低大約4個數量級，而其崩潰電壓也可提高約2 V。 本論文接著利用兩種新穎的矽前驅物(precursor)以金屬有機氣相沉積法製備高介電常數鉿的矽酸鹽。兩種矽前驅物分別是叔丁基二甲基矽醇(tert-butyldimethyl silanol)，與三叔戊氧基矽醇(tris(tert-pentoxy) silanol)。此論文研究的兩種矽前驅物在常溫常壓下為液態，因此可以提供足夠的蒸氣壓。兩種前驅物中，實驗發現三叔戊氧基矽醇此前驅物不需要氧氣介入反應即可生成矽酸鉿薄膜，而且可以在250 □C的低溫下生成平坦的矽酸鉿絕緣層。在此研究中，我們使用一組具備臨場(in situ)製程能力的高真空系統，沉積過程中利用臨場橢圓儀(Ellipsometer)觀察絕緣層成長，探討其成長機制，並利用臨場熱退火與電子能譜儀(XPS)研究薄膜材料特性。其後製作電容元件探討絕緣層之電特性，將薄膜結構變化與電特性比較。此絕緣層被製作成電容探討其電特性，在氫氮混和氣體下(4 % H2 + 96 % N2)經過450 □C退火，絕緣層介面特性獲得良好的改善。 利用臨場製程系統，本論文接著研究矽奈米微晶粒的製備。使用電子束蒸鍍法可在薄氧化層上沉積均勻且平坦的超薄(0.9□3.5 nm)非晶矽層。隨後在未破壞真空的條件下進行臨場快速熱退火(850 □C, 5min)，可以形成自組裝半球狀矽奈米微晶粒。原子力顯微鏡，電子顯微鏡與電子能譜儀被使用於觀察晶粒結構。在較低溫度下(750 □C)可以觀察到未完成的奈米點聚合現象。奈米晶粒先在非晶矽表面成核，接著聚合成較大的晶粒並消耗周圍的非晶矽層，直到其底部與二氧化矽基底層接觸。較薄的非晶矽層可形成較小且較密的晶粒。此研究中得到最小的晶粒半徑約是5.1 nm，同時亦得到最高的晶粒密度3.9×1011 cm-2。本論文亦利用臨場電子能譜觀測方法建立一套模型，以信號的強度估計矽奈米微晶粒的尺寸與密度，與實驗結果比較下，驗證出此方法十分具有實用性。 最後我們將此種新穎的半球狀矽奈米微晶粒製作成記憶體元件。製作矽奈米微晶粒於4nm之穿隧氧化層上，再覆蓋以17 nm之阻擋氧化層，製作完成之電容元件觀察到高的電荷儲存密度4.1□1012 cm-2 (電子+電洞)。將此矽奈米晶粒製作成非揮發性記憶體元件可得到良好的記憶體特性。在□10 V，0.02/0.1 s的閘極操作電壓下，可以得到約0.9 V之臨限電壓變化，在讀寫操作10000次之後亦保持住同樣的電壓記憶窗(memory window)。在□15 V的操作下則可以得到約2.8 V的臨限電壓變化量，驗證此矽奈米微晶粒在記憶元件上之實用性。實驗證明這種真空聚合法形成之矽奈米晶粒可應用於非揮發記憶體的製作。

In this dissertation, three approaches to incorporating nitrogen in CoTiO3 high-□ dielectric films, including the ion implantation of N2+, ion implantation of N+, and N2O plasma treatment, have been investigated. Nitrogen incorporation by ion implantation of N2+ can improve the electrical properties in terms of gate leakage, breakdown voltage and time-to-breakdown (TBD). To reduce the impinging mass of implanted ion species, N+ ion implantation has been used. The same trends can be found as those produced using N2+. A N2O plasma treatment is also an excellent method to improve the electrical properties, exhibiting better-behaved C-V curves, lower gate leakage currents and higher breakdown voltages. Two silanol precursors, tert-butyldimethyl silanol (BDMS) and tris(tert-pentoxy) silanol (TPOS), are evaluated as silicon precursors for hafnium silicate deposition with tetrakis-(diethylamido) hafnium (TDEAH). BDMS has one OH group, which should react with chemisorbed TDEAH. However, the other t-butyl and methyl groups can passivate the substrate surface, and stop the further absorption of TDEAH. Carbon-free hafnium silicate thin-films are deposited by MOCVD using alternative pulses of TDEAH and TPOS precursors. Hafnium silicates with high silicon contents (Hf1-xSixO2, x >0.5) are deposited at 250 □C without additional oxidants. MOS capacitors are fabricated for electrical characterizations. A forming gas anneal can improve the hafnium silicate interface quality. This low-temperature process could be promising for TFT or optoelectronic applications. Hemispherical Si nanocrystals are self-assembled using an in-situ thermal agglomeration technique. Ultrathin (0.9–3.5 nm) a-Si films are deposited on a 4-nm tunnel-oxide layer using electron-beam evaporation. An in-situ annealing can then activate the thermal agglomeration of Si and transform the ultrathin a-Si films into Si nanocrystals. The Si agglomeration process is evaluated with various processing parameters such as annealing temperatures, surface oxide conditions, and initial Si film thickness. Also, it is demonstrated that XPS measurements can effectively provide the information of the nanocrystal agglomeration. Calculations are made based on the photoelectron attenuation theories, and a simple model is proposed. Comparisons between the calculated results and the experimental data have shown a fairly good match. The fabrication of a Si nanocrystal-embedded nonvolatile memory has been demonstrated using a thermal agglomeration technique. MOS capacitors and MOSFETs embedded with hemispherical Si nanocrystals are fabricated and characterized. A stored charge density of 4.1□1012 cm-2 (electron + hole) is obtained with a highest nanocrystal density of 3.9□1011 cm-2. Uniform FN tunneling is used to program and erase the Si nanocrystal floating-gate n-MOSFETs. A Vt window of 0.9 V is achieved under P/E voltages of □10 V for 0.02/0.1 s. The memory device also shows good endurance and charge retention behaviors after 10000 P/E cycles. Increasing P/E voltages to □15 V creates a large memory window (>2.7 V) with the proposed memory device. After a retention test for 100 hours, a memory window of 1 V is maintained. The retention characteristics have shown little temperature dependence with the Si nanocrystal memories, indicating that the charge-loss process is determined by the direct tunneling from nanocrystals into the oxide/Si-substrate interface states.