完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | 丘兆仟 | en_US |
dc.contributor.author | Chao-Chian Chiu | en_US |
dc.contributor.author | 冉曉雯 | en_US |
dc.contributor.author | Hsiao-Wen Zan | en_US |
dc.date.accessioned | 2014-12-12T02:46:39Z | - |
dc.date.available | 2014-12-12T02:46:39Z | - |
dc.date.issued | 2004 | en_US |
dc.identifier.uri | http://140.113.39.130/cdrfb3/record/nctu/#GT009224576 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/76770 | - |
dc.description.abstract | 複晶矽薄膜電晶體在面板技術的應用上,由於其具有高遷移率,可以實現系統面板(System on Panel)的技術。為了要將周邊電路直接以複晶矽薄膜電晶體實現在玻璃基板上,與面板矩陣電路結合成所謂的系統面板,所以一個準確的元件物理模型是最重要的基礎。在本論文內,我們特別著重在複晶矽薄膜電晶體中,晶粒邊界位障(Grain boundary barrier)效應的研究。 首先,我們將元件處於各種不同的偏壓狀態,來研究此時的活化能特性,並提出一個新的活化能模型。然後,利用變化不同的通道長度和不同的薄膜品質,來萃取出模型中的各個參數。根據基本的元件模型和我們所研究的晶粒邊界位障效應,推導出元件的電性模型。模型產生的電性,可以準確描述元件在通道長度5.5 □m – 31.5 □m的輸出特性。除了基本的電流輸出特性,我們也分析元件的載子遷移率和通道表面平坦度在不同偏壓下的變化,並利用前述的模型解釋晶粒邊界位障所造成的影響。 另外,我們觀察到了缺陷密度對於閘極電壓和通道厚度之間的關係有很大的影響。藉由製作不同品質的複晶矽薄膜,來清楚的探討這個現象,並建立模型來加以解釋。同時,我們也利用了元件模擬軟體來加以比較缺陷密度所產生的影響。最後,我們成功建立了包含薄膜差異性、不同操作偏壓下對於元件特性影響的模型。 | zh_TW |
dc.description.abstract | Polycrystalline silicon thin-film transistors (TFTs) have been studied extensively for their applications on system-on-panel (SOP) technology. In order to integrate the peripheral driving circuitry onto the glass substrate, the accurate physical-based model for circuit design and simulation is needed. In this thesis, we especially focus on the analysis of grain boundary barrier effect in polycrystalline silicon thin-film transistors. Firstly, the conduction behavior of Poly-Si TFTs had been carefully studied by analyzing their activation energy under different bias condition, and a new activation energy model has been proposed. Then, activation energy model parameters were extracted from devices with various channel length and film quality. An accurate I-V model was established by combining basic TFT model and the grain boundary barrier effects. The model had been verified for devices with channel length varied from 5.5 □m to 31.5 □m. The mobility and scattering behavior are also well explained by our proposed model. The trapped charge screening effect of poly-Si film is also observed when the devices with large defect densities. We used various film quality devices to clarify this effect and established adequate model to explain this phenomena. Finally, the influence of defect densities on the dependence between grain barrier and gate bias was examined by device simulation results. Good agreements are found when comparing the simulated results and the experimental results. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | 複晶矽 | zh_TW |
dc.subject | 薄膜電晶體 | zh_TW |
dc.subject | 晶粒邊界位障 | zh_TW |
dc.subject | poly-Si | en_US |
dc.subject | TFT | en_US |
dc.subject | grain boundary barrier | en_US |
dc.title | 複晶矽薄膜電晶體晶粒邊界位障效應之研究 | zh_TW |
dc.title | The Analysis of Grain Boundary Barrier Effect in Polycrystalline Silicon Thin-Film Transistors | en_US |
dc.type | Thesis | en_US |
dc.contributor.department | 光電工程學系 | zh_TW |
顯示於類別: | 畢業論文 |