固態晶體Nd:YAG雷射結晶之複晶矽薄膜電晶體結晶機制分析與載子傳輸模型建立

Abstract

近年來低溫複晶矽薄膜電晶體已經引起大量的研究，其應用的方向是相當廣泛的。為了得到高品質的低溫複晶矽，雷射再結晶與其他結晶技術相比，是十分大有可為的。在本論文內，我們特別著重在經由高瓦數固態晶體Nd:YAG雷射再結晶的複晶矽薄膜，其結晶機制的分析與探討，以及從薄膜本身的特性，建立出以物理意義為根本的載子傳輸模型。 首先，經由高瓦數固態晶體Nd:YAG雷射再結晶的複晶矽薄膜，藉由分析其拉曼訊號以及電子掃描式顯微鏡圖形，完整的結晶機制已經被仔細的研究和探討。其發現到高斯分佈的雷射投射光波形，能成功的產生大的側向結晶製程區域。在此製程區域內，元件的載子傳輸率高達約250 cm2 / Vs，而且臨界電壓小於1 V。非晶矽薄膜的厚度以及雷射掃瞄的重疊範圍對製程區域大小的影響也有被仔細的研究。另外，我們也成功的利用高瓦數固態晶體Nd:YAG雷射，再結晶出高品質的複晶矽鍺薄膜。矽鍺波峰的半高寬約為23.68 cm-1，非常接近的單晶矽鍺的半高寬。 我們提出以物理意義為根本的載子傳輸模型，其中包含了晶粒邊界能障效應與聲子晶格散射效應。其只利用幾個模擬參數，就能準確的推測電子傳輸率在各種閘極偏壓下的大小。此載子傳輸模型在元件通道長度30 μm - 6 μm，通道寬度為6 μm時，溫度從298 K變化到343 K下，皆能正確的描述出元件的特性。更進一步的，我們採用所提出的載子傳輸模型去模擬元件的電流電壓輸出特性，其模擬結果與實驗數據都相當的吻合。

Recently, low temperature polycrystalline silicon thin-film transistors (TFTs) have been investigated extensively for their wide applications. In order to achieve high quality poly-Si at low process temperature, laser crystallization technology is a promising method compared with other techniques. In this thesis, we especially focus on the analysis on crystallization mechanism of poly-Si annealed by high power solid-state Nd:YAG laser and establish physically-based mobility model including temperature effect directly through thin film property. Firstly, the poly-Si crystallization mechanism under the high power (200 W) Nd:YAG solid state pulsed laser annealing system have been carefully studied by analyzing their Raman spectra and scanning electron microscope . It is found that the Gaussian-distributed laser beam profile successfully produce large super lateral growth process window. The devices in the SLG process window exhibit field-effect mobility around 250 cm2 / Vs and the threshold voltage lower than 1 V. The influence of a-Si film thickness and the laser scan pitch on the process window is also carefully inspected. In addition to poly-Si, high quality poly-SiGe annealed by SSL has been successfully achieved. The FWHM value of Si-Ge peak is about 23.68 cm-1 which is close to single crystal SiGe alloy. The physically-based mobility model containing grain barrier height effect and phonon lattice scattering effect have been proposed. It can precisely predict the mobility over wide range of gate voltage bias by using only few fitting parameters. The model is valid for devices with channel length varying from 30 μm to 6 μm while channel width is 6 μm under a temperature range from 298 K to 343 K. Moreover, we adopt the proposed mobility model to simulate output characteristics of devices. Excellent agreements are found when comparing the calculated results and experimental data.