低溫多晶矽薄膜電晶體數位電路變動性之模擬研究

Abstract

複晶矽薄膜電晶體(poly-Si TFT)最近幾年在液晶顯示器(AMLCD)應用中之所以會是眾所注目的焦點，是因為其優異的元件特性。相較於非晶矽薄膜電晶體，複晶矽薄膜電晶體有較高電流驅動能力及較好的可靠度,因此在複晶矽薄膜電晶體顯示器裡，它可以被用來整合畫素電路及週邊驅動電路於同一片玻璃基板上，如此使面板結構簡單化且可以減少週邊半導體零組件的使用數量以及後段模組在組裝時的接點數目，進而提高工程可靠度，除此之外更可降低驅動IC成本，維持低耗電特性，提供高精細的畫質表現。所以，複晶矽薄膜電晶體被視為實現系統化面板(System on Panel)的關鍵技術。然而，由於複晶矽層不規則的晶粒邊界分佈，複晶矽薄膜電晶體有較差的均勻性，同時元件參數呈現大範圍變動。 在本篇論文，我們先描述元件的變動，並進一步研究其對於數位電路的影響以及如何使用模擬技巧來預估電路效能的課題。本篇論文的目的為開發一個新的模擬技巧，係利用一級移位暫存器之傳播延遲時間與功率消耗來預測N級操作頻率及功率散失。

Polycrystalline silicon (poly-Si) thin film transistors (TFTs) have recently attracted much attention in the application on the integrated peripheral circuits of active matrix liquid crystal displays (AMLCDs). The significant advantages over amorphous silicon (a-Si) TFTs are in the higher current driving capability and the better reliability. In poly-Si TFT-controlled displays, poly-Si TFTs are used to implement pixel circuits and driving circuits on a single glass substrate to reduce system cost and posses compact module. Therefore, the poly-Si TFT is the best candidate to realize system-on-panel (SoP). However, due to the irregularly distributed grain boundary, poly-Si TFTs have poor uniformity and suffer from huge variation. In this thesis, the device variation is described. Its influences on the digital circuits and circuit simulation techniques to estimate the circuit performance are also discussed. The purpose of this thesis is to develop a new simulation skill that the operation frequency and power consumption of an n-stage shift register can be obtained through simplifying propagation delay from an n-stage one to an one-stage one.