先進金氧半場效電晶體對於佈局之依賴效應

Abstract

次100奈米先進互補金氧半技術中之金氧半場效電晶體對於佈局的依賴效應已經日趨明顯。本篇論文展示了兩個主要引起金氧半場效電晶體行為對於佈局依賴性的要素 ­ 製程引起的機械應力效應和井邊緣親近效應。 在製程引起的機械應力效應方面，第一點，本論文使用閘極長度為65奈米的先進互補金氧半技術完成了實驗之設計與執行。第二點，以包含種種機械應力來源並考慮全製程的數值運算完整的模擬了整個金氧半場效電晶體結構。第三點，提出了一個新的應力相依的摻雜擴散模型並將之加入於數值模擬軟體中，而模擬結果符合了矽晶片實驗實驗範圍內之金氧半場效電晶體的次臨限(subthreshold)特性。第四點，本論文探討了淺溝渠及熱氧化製程引起的機械應力和金氧半場效電晶體開狀態(on-state)對於佈局的依賴效應的關係，發展出一組精簡、可變化規模(scalable)的新積體電路模擬程式(SPICE)模型來解釋淺溝渠機械應力對金氧半場效電晶體性能的影響，並且成功預測晶片實驗中各條件的實驗結果。 本論文亦使用了次100奈米先進互補金氧半技術詳細探討了由離子佈植時邊界摻雜散射引起的井邊緣親近效應。晶片實驗和技術電腦輔助設計(TCAD)模擬被用來從物理和製程的角度探討這個效應。蒙地卡羅離子散射模型和技術電腦輔助設計模擬提供了金氧半場效電晶體內部如何形成改變的物理了解。一個基於此物理了解的精簡新積體電路模擬程式模型被提出來並且以晶片實驗中各測試組結果完成此模型之校正。

The layout dependent effect on the MOSFETs characteristics has become more and more significant in advanced sub-100nm CMOS technologies. This dissertation demonstrates the experimental results, theories and modeling of two main factors making MOSFET behaviors layout dependent – process induced mechanical stress effect and well-edge proximity effect. For the process induced mechanical stress effect, first, complete experiments are designed and conducted using novel CMOS technology with a minimum physical gate length of 65nm to investigate the mechanical stress effect. Second, full-process numerical simulations are performed for modeling complete MOSFET structures containing various mechanical stress sources. Third, a new stress-dependent dopant diffusion model is proposed and is implemented into the simulation software and the simulation results match MOSFET subthreshold characteristics of the silicon wafer experiment within the design space. Fourth, the relationship between layout dependence of MOSFET on-state characteristics and mechanical stress caused by shallow trench isolation (STI) and thermal oxidation has been investigated, and a new compact and scaleable SPICE model accounting for the STI mechanical stress effect on MOSFET electrical performance is developed and successfully matches the experimental data under various conditions. The well-edge proximity effect caused by the boundary dopant scattering during ion implantations is further explored using a sub-100nm CMOS technology in detail. TCAD simulations together with silicon wafer experiments have been conducted to investigate the impact of this effect from a physics and process perspective. The Monte Carlo ion scattering model and TCAD simulations provide a physical understanding of how the internal changes of the MOSFETs are formed. A new compact model for SPICE is proposed using physics-based understanding and has been calibrated using experimental silicon test sets.