完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | 林育成 | en_US |
dc.contributor.author | Yu-Cheng Lin | en_US |
dc.contributor.author | 李榮貴 | en_US |
dc.contributor.author | Rong-Kwei Li | en_US |
dc.date.accessioned | 2014-12-12T02:49:56Z | - |
dc.date.available | 2014-12-12T02:49:56Z | - |
dc.date.issued | 2006 | en_US |
dc.identifier.uri | http://140.113.39.130/cdrfb3/record/nctu/#GT009263512 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/77601 | - |
dc.description.abstract | 投片到產出的時間稱為生產週期(Cycle time),半導體產品從投入到產出通常需一到二個月的時間。因為對市場的反應時間很長,所以生產週期一直是晶圓代工廠影響客戶滿意度的重要指標之一,不良的生產週期常造成客戶抱怨,甚至訂單流失;而且半導體工廠的投資額高,生產週期代表的是資金的堆積。所以晶圓代工廠一直都投注大量人力於生產週期的管理與改善。 一般工廠做生產週期的管理通常只是根據經驗訂定Turn Rate及標準在製品量(STD WIP),再據以拉貨和消WIP,沒有一套較完整的生產週期管理理論。當工廠狀況改變,如產品組合改變或產能使用率改變,此時根據Little’s law可以預知生產週期及在製品量將會跟著改變,過去經驗也跟著不適用。目前絕大多數的工廠並無法反應此狀況,以至於產品組合改變或產能使用率改變都須經過一段爭執的陣痛期,當情況穩定時,經驗能派上用場,管理才又上軌道。 本論文期望發展出一套計算標準在製品(STD WIP)的方式,再利用SPC (Statistical Process Control)的觀念,訂定WIP上下限,當超出上下限則採取適當的派工以修正WIP Profile ,如此可以降低WIP水位,生產週期也得以逐步降低。 | zh_TW |
dc.description.abstract | The definition of cycle time is the time from the wafer start to the wafer output. It usually takes one or two months to get the product since customer decides to produce it. Cycle time is a critical factor for customer satisfaction because it represents the response time to the market. Long cycle time also reflects the ineffective investment for the capital. Cycle time is very important for foundry because long cycle time will cause customer unsatisfied and the order loss. Consequently, all of the foundries put lots of human source in the cycle time improvement. Usually, we make decisions based on the experience in cycle time management. We have no mechanism or theory for cycle time management. We do WIP management based on turn rate and standard WIP set by experiences. But the experience didn’t mean the optimal solution, when the situation changed, the cycle time or the standard WIP will also be changed. The experience will not always be applicable. If we only have the experience and no mechanism, management will not be work out. After interview several foundry fab managers, all of the fab can’t reflect the situation. That is, all of them will have an impact period after product mix or utilization varied. In this study, we want to develop a formula for standard WIP and use SPC concept to set WIP upper/lower limit. When WIP exceed the limit, it will trigger action plans to compensate WIP profile. If WIP profile balances, we don’t need too much WIP. So WIP level could be reduced and cycle time also could be reduced. | en_US |
dc.language.iso | zh_TW | en_US |
dc.subject | 晶圓代工 | zh_TW |
dc.subject | 生產週期時間 | zh_TW |
dc.subject | 達交率 | zh_TW |
dc.subject | 派工 | zh_TW |
dc.subject | 在製品管理 | zh_TW |
dc.subject | Foundry | en_US |
dc.subject | Cycle Time | en_US |
dc.subject | Delivery | en_US |
dc.subject | Dispatch | en_US |
dc.subject | WIP Management | en_US |
dc.title | 以WIP SPC改善晶圓代工廠生產週期之個案研究 | zh_TW |
dc.title | The Study of the Cycle Time Improvement by WIP SPC for IC Foundry Manufacturing | en_US |
dc.type | Thesis | en_US |
dc.contributor.department | 管理學院工業工程與管理學程 | zh_TW |
顯示於類別: | 畢業論文 |