非直接傳輸波動導管式之電流型類比至數位轉換器之設計

Abstract

本論文中，提出並分析了非直接傳輸波動導管式之電流型八位元解析度類比至數位轉換器之設計，它克服了在傳統導管式之電流型類比至數位轉換器中的速度限制。在本論文中，利用了許多特性包括全差動式的架構與每一級2.5位元結合數位錯誤校正，對於高精確度電流比較器的新偏差校準法則，以及可調式電壓控制延遲線用於適度地控制類比與數位訊號處理之間的同步時程，..等等，實現了更高轉換速率與有效的時間運用。在所採用的電流型類比至數位轉換器中，並不須要使用線性電容，所以它可是完全相容於CMOS數位製程。 本論文中採用之八位元解析度電流型類比至數位轉換器的實驗晶片，係透過國家晶片系統設計中心委託台灣積體電路製造股份有限公司，以0.18微米1P6M互補式金氧半導體的製程製造。其晶片尺寸是1.96 x 2.09mm2。在 1.8V的供應電壓下，此製成的晶片的量測結果，經過校正對於通道偏差與增益的不匹配，顯示在每秒100百萬取樣的轉換速率下，其DNL、INL是1.9和1.8 LSB，SNDR是36.8dB，ENOB是5.8位元，功率消耗是123毫瓦。最高的轉換速率達到每秒125百萬取樣ENOB是5.2位元。 總而言之，在本論文中所採用的非直接傳輸波動導管式之電流型類比至數位轉換器，已經被成功的驗證在電腦模擬與製成晶片實驗量測的結果。與先前的其它成果相比較，本論文中所採用的架構以及電路實現，在速度效能上獲得了顯著的改善。我們相信，在本論文中所採用的非直接傳輸波動導管式之電流型類比至數位轉換器之設計，在未來的高速電流型類比至數位轉換器之設計上，能夠提供前瞻的效能表現。

In this thesis , the design of Indirect Transfer Wave-Pipelined current-mode analog-to-digital converter (ITWP-IADC) with 8-bit resolution is proposed and analyzed to overcome the speed limitations in the conventional pipelined IADC . It employs some features including the fully differential architecture with 2.5-bit per stage combining the digital error correction , new offset calibration algorithm for high precision current comparator and the voltage controlled delay lines (VCDL) for adaptive controlling the synchronous timing for analog and digital signals processing , ..etc , performing the higher conversion rate and the effective timing usage . The linear capacitor is not required in the proposed IADC , so it is fully compatible with standard CMOS digital process . The experimental chip of the proposed ITWP-IADC with 8-bit resolution was fabricated in a 0.18um 1P6M CMOS technology supported by Taiwan Semiconductor Manufacturing Company via Chip Implementation Center . The chip size was 1.96 x 2.09 mm2 . With 1.8V supply voltage , the measurement results of the fabricated chip which the channel offset and channel gain mismatches are calibrated , shows the DNL , INL are 1.9 and 1.8 LSB , the SNDR is 36.8dB , ENOB is 5.8-bit under the sampling rate of 100MS/s , the power dissipation is 123mW . The highest conversion rate reaches to 125MS/s , ENOB is 5.2-bit . In summary , the proposed ITWP-IADC in this thesis has been verified by computer simulations as well as experimental results measured from fabricated chip . As compared to prior works , significantly improvement of the speed performance has been obtained by using the proposed architecture and circuits implementations . It is believed that the proposed ITWP-IADC offers promising performance for future design of high speed IADCs .