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dc.contributor.author陈永裕en_US
dc.contributor.authorYeong-Yuh Chenen_US
dc.contributor.author罗正忠en_US
dc.contributor.author简昭欣en_US
dc.date.accessioned2014-12-12T02:50:35Z-
dc.date.available2014-12-12T02:50:35Z-
dc.date.issued2004en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#GT008611512en_US
dc.identifier.urihttp://hdl.handle.net/11536/77790-
dc.description.abstract随着系统晶片(SOC)的发展,持续降低CMOS元件中的闸极介电层及非挥发性记忆体中的复晶矽层间介电层(inter-poly dielectric)厚度以提高元件密度及降低操作电压变得十分重要。为了满足以上的需求并获得较低的漏电流及较高的可靠度,利用氮氧化层(nitrided oxide)及高介电常数材料(high-□)来取代二氧化矽变成是不可或缺的趋势。
本篇论文首先研究利用成长氧化层前的氮原子离子布植(nitrogen-implanted Si substrate)及氧化层成长后的一氧化氮(NO)高温退火来改善传统二氧化矽闸极介电层的可靠度。其次,经由模拟工具将高介电常数材料做为堆叠式快闪记忆体(stacked-gate flash memory)的复晶矽层间介电层和穿隧介电层(tunnel dielectric),并讨论其对快闪记忆体写入/抹除的效率。最后,探讨表面氨气(NH3)氮化处理及沉积后高温退火(post-deposition annealing)温度对反应式溅镀(reactive sputtering)及有机金属化学气相沉积(metal organic chemical vapor deposition)之高介电常数材料三氧化二铝(Al2O3)及二氧化铪(HfO2)复晶矽层间电容的影响。
首先,研究利用成长氧化层前的氮原子离子布植及氧化层成长后的一氧化氮高温退火来改善传统二氧化矽闸极介电层的可靠度。研究结果显示成长后的一氧化氮高温退火会在界面处造成氮原子聚集,而成长氧化层前的氮原子离子布植则会造成氮原子均匀分布在氮氧化层里。掺杂进入氧化层的氮浓度也会随着氧化层厚度而变;氧化层厚度愈薄,氮浓度愈高。聚集在界面处的氮原子有助于增强二氧化矽介电层的可靠度,包括较平整的界面、较小的电洞捕捉(hole trapping)、改善崩溃时间(time-to-breakdown)及崩溃电荷(charge-to-breakdown)等。此外,介电层的可靠度还可由氮离子布植浓度决定。当浓度小于1□1014 cm-2时,氧化速率不但不会降低,还会造成介电层可靠度劣化;相反的,若将浓度提高至1□1015 cm-2,氧化速度可以很明显的被抑制并用来成长多种不同介电层厚度以满足系统晶片需求,还可同时改善介电层可靠度。配合成长氧化层前的氮原子离子布植和氧化层成长后的一氧化氮高温退火更可大幅提高闸极介电层的可靠度,用以取代0.13微米以下制程的二氧化矽闸极介电层。
其次,经由模拟工具将高介电常数材料做为堆叠式快闪记忆体的复晶矽层间介电层和穿隧介电层,并讨论其对快闪记忆体写入/抹除的效率。模拟结果指出利用高介电常数材料取代传统堆叠式快闪记忆体中的氧化层-氮化层-氧化层(oxide-nitride-oxide)复晶矽层间介电层可明显的提高写入/抹除的速度,且写入/抹除的速度在Fowler-Nordheim穿隧上比热电子(hot electron)注入的方式更有效。选择二氧化铪做为复晶矽层间介电层并采用Fowler-Nordheim穿隧来写入/抹除,可大幅降低外加电压达48%。然而,高介电常数材料在穿隧介电层上的应用结果却截然相反。由于采用高介电常数材料做为穿隧介电层会降低闸极的电压藕合率(gate coupling ratio),利用Fowler-Nordheim穿隧反而会劣化写入/抹除速度。虽然分压在高介电常数穿隧介电层的电场会比传统二氧化矽穿隧介电层的电场还低,但较低的电子位障高(barrier height)及增强的碰撞游离发生率(impact ionization rate)却使得高介电常数穿隧介电层在热电子注入方式下有较快的写入/抹除速度。由于适用的写入/抹除方式不同,高介电常数材料复晶矽层间介电层及穿隧介电层可分别应用于NAND和NOR型式的堆叠式快闪记忆体。
最后,探讨表面氨气氮化处理及沉积后高温退火温度对反应式溅镀及有机金属化学气相沉积之高介电常数材料三氧化二铝及二氧化铪复晶矽层间电容的影响。表面氮化处理和高温退火温度都会造成反应式溅镀的三氧化二铝复晶矽层间电容的特性和电压极性相关。表面氮化处理会在界面处形成薄Si-N界面层,抑制低介电常数界面层成长、形成较平滑的界面并让后续的高温退火更有效率的消除原本存在的缺陷,得到较低的漏电流、较大的崩溃电场、较小的电子捕捉率和较大的崩溃电荷。再者,反应式溅镀的三氧化二铝复晶矽层间电容的特性也受高温退火温度影响甚巨。实验结果显示,不论是漏电流、电子捕捉率或崩溃电荷,900oC都是最佳化条件。根据X光光电子频谱(X-ray photoelectron spectroscopy)和Auger电子频谱(Auger electron spectroscopy)的分析,发现温度效应会造成三氧化二铝的组成比发生明显的变化,其中氧原子的成份比将会决定复晶矽层间介电层的特性。有鉴于反应式溅镀的三氧化二铝复晶矽层间电容的崩溃电荷过低,我们也研究利用有机金属化学气相沉积方式沉积三氧化二铝和二氧化铪来改善崩溃电荷的可能性。实验结果证明,利用有机金属化学气相沉积除了可大幅改善崩溃电荷外,也能有效的降低漏电流和增加崩溃电压(breakdown voltage)和有效崩溃电场(effective breakdown field)。因此,等效氧化层厚度为5奈米及3奈米的三氧化二铝和二氧化铪将是45奈米及32奈米世代以下堆叠式快闪记忆体的绝佳候选复晶矽层间介电层。
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dc.description.abstractFor the system on a chip (SOC) application, a continuously scaling of the gate dielectrics for complementary metal oxide semiconductor (CMOS) and inter-poly dielectrics (IPDs) for electrically-erasable programmable read only memory (EEPROM) and stacked-gate flash memory is needed to obtain high density and low operation voltage. To meet the above requirements and exhibit a low leakage current and a good reliability, the replacement of nitrided oxides and high dielectric constant (high-□) materials for the silicon dioxide (SiO2) and additional treatment have become indispensable.
The first objective of this dissertation is to apply the pre-oxidation nitrogen implanted Si substrate (NIS) and post-oxidation nitric oxide (NO) annealing to improve reliabilities of conventional SiO2 gate dielectric. Then, investigates the impact of high-□ materials serving as the IPDs and tunnel dielectrics (TDs) on the programming/erasing performances of stacked-gate flash memories through 2-D Medici simulation. Finally, the surface NH3 nitridation and post-deposition annealing (PDA) temperature effects of the reactive-sputtered (RS) and metal organic chemical vapor deposition (MOCVD) high-□ IPDs is studied.
Firstly, we focused on the dielectric characteristics and reliability phenomena of NIS nitrided oxides with NO- and N2-annealing comparing to conventional SiO2 gate oxide. It was found that a nitrogen pile-up occurred near the interface after NO-annealing, while NIS produced a uniform nitrogen distribution in the dielectric bulk. Incorporated nitrogen atomic concentration is also affected on the initial oxide thickness; thinner oxide thickness, higher nitrogen atomic concentration. Nitrogen pile-up near the interface is beneficial to enhance dielectric reliabilities in terms of smoothen interface roughness, reduced hole trapping, improved time-to-breakdown (tBD) and charge-to-breakdown (QBD). Moreover, it was found that the dielectric reliability is strongly dependent on the NIS dosage. NIS with a dosage smaller than 1□1014 cm-2 is found to be useless in the oxidation rate suppression but degrades dielectric reliability simultaneously. On the contrary, the samples with 1□1015 cm-2 NIS dosage not only exhibit a significantly reduced oxidation rate, which can be used to grow multiple oxide thicknesses to meet the SOC requirement, but also improve stress immunity. NIS nitrided oxides with NO-annealing depict superior dielectric reliability and this technique appears suitable to replace the traditional SiO2 at 0.13 □m technology node and beyond.
Secondly, the effects of high-□ IPDs and TDs on a flash memory performance will be presented. By 2-D MEDICI simulation, flash memories with high-□ IPDs clearly exhibit significant improvement in programming/erasing speed over those with conventional ONO IPD. Moreover, it is found that high-□ IPDs are more effective for the memories programmed/erased with Fowler-Nordheim (FN) tunneling rather than channel hot electron (CHE) injection. Choosing HfO2 as the IPD and using F-N programming/erasing scheme, the operating voltage can be reduced 48% at a typical program time of 10 □s and 0.1 ms erasing time. Our results also show that dielectrics with very high permittivity (□ > 25) may not be necessary for the IPD in stacked-gate flash memories. On the other hand, the effect of high-□ TDs is quite contrary to the high-□ IPDs. Due to the reduced gate coupling ratio, the programming/erasing speed of stacked-gate flash memories with high-□ TDs by using FN tunneling is helpless in operation voltage reduction. Although the electric field on high-□ tunnel dielectrics is lower than SiO2 tunnel oxide, enhanced impact ionization rate and lower barrier height contribute to higher CHE injection current and efficiency. Consequently, high-□ TDs are only effective for the memories programmed/erased with hot electron injection rather than FN tunneling. Due to the contrary programming/erasing schemes, high-□ IPDs and TDs are suitable for NAND- and NOR-type stacked-gate flash memories, respectively.
Finally, the effects of surface NH3 nitridation of the bottom poly-Si film and PDA temperature on the electrical properties and reliability characteristics of RS and MOCVD high-□ inter-poly capacitors were evaluated. The polarity-dependent dielectric properties of RS Al2O3 IPD were strongly affected by the surface nitridation and the annealing temperature. For positive gate bias, IPD with NH3 surface nitridation were found to significantly suppress the formation of an additional layer with lower dielectric constant during the post-annealing process and obtain a smoother interface, compared to those without nitridation treatment. Furthermore, the presence of a thin Si-N layer can make PDA more effective in eliminating traps existing in the as-deposited films and improve dielectric characteristics under negative polarity. As a result, the smoother interface and smaller electron trapping rate contribute to the drastically reduced leakage current, enhanced breakdown field, and QBD of the RS Al2O3 inter-poly capacitors with surface NH3 nitridation. Moreover, the electrical properties of RS Al2O3 IPD are heavily dependent upon the PDA temperature. The sample exhibits optimal quality in terms of leakage current, electron trapping rate and QBD when annealed at 900°C. X-ray photoelectron spectroscopy and Auger electron spectroscopy analyses have shown that this occurrence arises from the composition variations under different annealing conditions and excess oxygen, which can act as an electron trapping center, playing an important role in determining the IPD electrical properties. The results apparently demonstrate Al2O3 IPD with surface nitridation and optimized PDA temperature can effectively reduce charge transfer between CG and FG, better retention and disturb characteristics are expected by replacing ONO IPD to Al2O3 IPD. MOCVD Al2O3 and HfO2 IPD are investigated in order to further promote QBD of RS Al2O3 IPD. The QBD can be significantly improved as well as reduced leakage current density, enhanced breakdown voltage and effective breakdown field by using MOCVD replacing RS. As thin as 5nm and 3nm EOT of Al2O3 and HfO2 IPD is suitable to meet the requirement of 45nm and 32nm generation stacked-gate flash memories, respectively.
en_US
dc.language.isoen_USen_US
dc.subject氮氧化层zh_TW
dc.subject高介电常数介电层zh_TW
dc.subject快闪记忆体zh_TW
dc.subjectnitrided oxideen_US
dc.subjecthigh-k dielectricen_US
dc.subjectflash memoryen_US
dc.title氮氧化层及高介电常数介电层在金氧半元件及快闪记忆体上之特性研究zh_TW
dc.titleInvestigation of Nitrided Oxides and High-k Dielectrics on MOS Devices and Flash Memoriesen_US
dc.typeThesisen_US
dc.contributor.department电子研究所zh_TW
显示于类别:Thesis


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