多晶矽熔線熔斷條件分析研究

Abstract

電遷移現象（electron migration）在電子元件是相當不受歡迎，尤其在製程已微縮至微米（micro meter）等級之半導體元件，更是在設計上一大挑戰。因其會造成導線斷路，或是所產生之微絲（filament）與鄰近導線接觸而造成短路。但有一種特殊使用種元件－電熔線（efuse），卻是利用電遷移現象，讓所設計之導線在某特定能量條件下產生電遷移現象，將導線熔斷形成導線斷路，進而判斷其數位訊號改變（0或1）。 傳統利用電遷移現象所設計之電熔線多為金屬導線（metal fuse），為利用IC製程時所形成之金屬導線（鋁導線或銅導線），加以適當設計而成。其優點是在相對低電壓下即可將導線熔斷，缺點是佔用金屬導線面積，加大晶粒（chip）面積。隨著電路設計越趨複雜，所要求導線面積也增加，另一種電熔線－多晶矽熔線（poly fuse）也逐漸被導入使用。 多晶矽熔線，顧名思義就是用多晶矽導線來取代金屬導線作為熔線。其優點就是不需佔用金屬導線面積，但其缺點就是需相對高電壓並有可靠性疑慮（reliability concern），故在IC設計上所要考慮的地方比金屬導線要複雜。 本研究方向是以標準8吋晶圓0.35 um邏輯製程設計出不同長度多晶矽熔線，及植入不同雜質元素於多晶矽熔線中，交叉分析其阻值變化，求取最佳化熔斷條件。實驗結果： （1）若以熔線長度做分析，2 um長度最適合做為熔線。 （2）若以植入不同雜質元素於多晶矽熔線中做分析，對於不同長度熔線阻值並無明顯變化。 （3）根據熔線阻值變化，最佳化熔斷條件為：在電壓4 V時，通上電流60 mA，維持500微秒（micro second）。

Electromigration is unwelcome and challenged from designer, especially in integrated circuit (IC) design was going to micrometer generation. This defect causes the metal line broken, or the migrated metal atoms collection to generate a filament to short neighborhood metal line. But fortunately, this characteristic of electromigration can be used in a special device – electrical fuse (or e-fuse). It is designed a certain conductance line and is controlled by electrical power which can blow out the conductance line effectively. Designer can make a judgment easily between rupture line and enrapture line, which he can also assign the different signal for them. For example, rupture line is defined to “0”; enrapture line to “1”. Metal material, normally aluminum or copper, is popular used in e-fuse traditionally. It is formed in IC manufacturing with special design. The advantage is that fuse blow out with lower power and few site effects. The disadvantage is that region of material line is occupied and causes the chip size becomes bigger. Based on the circuit design complicate daily, the area of metal line request is increasing, another fuse – poly line fuse is introduced. The advantage of poly fuse improve metal pattern density, but shortage is that need more electrical power to rupture the poly line and with reliability concern. Another issue is complication for circuit design due to the line is manufactured in polysilicon forming which is one of frontend steps of thermal processing. This study is used 8 inch wafer with standard 0.35um logic process and split different condition, including poly line length and process dosage, to analysis the resistance variation. Finally to get the optimization condition to blow out poly line. Experiment summary: 1. The best poly line is 2.0 micrometer for 0.35um logic process. 2. Based on resistance date, it is unobvious in dosage for deferent poly length. 3. Recommendation of program condition: Program voltage (VPP): 3.3V +- 10% Program current (IPP): 65mA Program time: 500 us