利用準分子及連續波雷射退火製作高效能低溫複晶矽薄膜電晶體之研究

Abstract

近年來，低溫複晶矽薄膜電晶體是在顯示技術應用中的關鍵元件。雖然透過準分子雷射可有效的提升頂閘極低溫複晶矽薄膜電晶體複晶矽層的結晶性，但此方法仍有此許缺點，如它可能在主動層和介電層之間造成大的粗糙界面，也可能形成隨機的晶界分佈等等。在這篇論文裡，我們將提出三種方法來增進低溫複晶矽薄膜電晶體的特性。 在第一個部分，我們稱為位置控制單垂直晶界低溫複晶矽薄膜電晶體方法將被提出而加以探討。我們將介紹單晶界低溫複晶矽薄膜電晶體機制。因為底閘極結構邊緣台階區提供了較厚非晶矽層，在準分子雷射退火時表示出晶種的特性。當雷射能量密度控制使得較薄的元件通道區域全熔，且接近角落較厚的區域半熔，如此一來，由通道二邊側向成長的晶粒沿著相反的方向向通道中間成長，進而在通道的中心只形成一條垂直的晶界。因此，我們可以得到大型的晶粒，進而提升元件的效能。各種各樣的分析方法也將用來探討單垂直晶界低溫複晶矽薄膜層，由掃描式電子顯微鏡，穿透式電子顯微鏡和原子力顯微鏡的分析中可知，我們觀察到大約 0.75μm長的人工控制晶粒。 我們也加以研究了單垂直晶界低溫複晶矽薄膜電晶體的電特性，可完全與傳統底閘極低溫複晶矽薄膜電晶體製作流程相容的單垂直晶界低溫複晶矽薄膜電晶體將被製作出來，在沒有任何氫化的處理之下，其載子移動率更超過 250cm2 / V-s。我們也觀察到閘極引起的汲極漏電和紐結效應也減少了，同樣的元件的均勻性也被提升，在量測二十個元件之下，載子移動率的標準差小於30cm2/V*s ，臨界電壓的標準差小於0.5 V。而且在沒有任何可靠度衰退之下（如在傳統的頂閘級元件中較低的崩潰電場），單垂直晶界低溫複晶矽薄膜電晶體更適用於較薄的閘極氧化層。因此，高性能單垂直晶界低溫複晶矽薄膜電晶體可在無任何特殊結構和材料的條件下單純利用較薄的閘極氧化層得到更佳的元件驅動能力與更陡直的的次臨界擺幅。 雖然單垂直晶界低溫複晶矽薄膜電晶體表現出良好的電特性，由於偏離的離子佈植使得不對稱的電特性成為其一大問題。因此在第二個部分中，我們將結合單垂直晶界低溫複晶矽薄膜電晶體方法與背後曝光法製作出新穎自我對準的單垂直晶界低溫複晶矽薄膜電晶體。非晶矽閘極層形成了如同光罩的效果，在微影製程下阻擋了來自於汞燈的紫外光，從光學顯微鏡和掃描式電子顯微鏡的分析中可看出，光阻可完美自我對準於非晶矽閘極層。除了單垂直晶界低溫複晶矽薄膜電晶體原本具有的良好特性外，自我對準的單垂直晶界低溫複晶矽薄膜電晶體也表現出對稱性良好的電特性。自我對準單垂直晶界低溫複晶矽薄膜電晶體載子遷移率可大約192 cm2 / V-s而在同樣的製程條件下的非自我對準元件卻大約只有 17.76 cm2 / V-s。閘極引起的汲極漏電和紐結效應也減少了。如此一來我們更能將自我對準的單垂直晶界低溫複晶矽薄膜電晶體應用於畫素電路中的開關元件。 可惜的是，在自我對準的單垂直晶界低溫複晶矽薄膜電晶體的通道中仍然有一垂直晶界。因此，新穎連續波雷射結晶法在本論文的第三部分被提出。首先，我們先探討了連續波雷射在摻雜活化的特性，我們發現以連續波雷射活化是一個低熱預算和高效率方法。其活化能力可使片電阻低於 47 Ω/□。接下來，我們也用連續波雷射結晶法製作出高效能n型和p型的低溫複晶矽薄膜電晶體。根據以前的研究中指出，利用連續波結晶法晶界將和雷射掃描的方法平行。如此一來，使用連續波雷射結晶法可製作出無高角度晶界的低溫複晶矽薄膜電晶體，而載子移動率在n型和p型中分別為192 cm2/V-s 和 92 cm2/V-s。另一方面，由於可完全與傳統頂閘極低溫複晶矽薄膜電晶體製作流程相容，因此製作流程十分簡單。加上由於連續波雷射結晶法掃描的速度很快，使得連續波結晶法低溫複晶矽薄膜電晶體的產出率上升，因此十分適合將來系統面板的應用 。

In recent years, low temperature polycrystalline thin film transistors (LTPS-TFTs) were the key devices in display applications. Although conventional top-gate LTPS-TFTs by excimer laser crystallization was an effective technology in improving the crystallinity of polycrystalline silicon thin films, there were still some drawbacks in conventional top-gate LTPS-TFTs such as high roughness interface between active layer and gate insulator, random grain boundaries and etc. In this thesis, we introduced three methods to improve the performance of LTPS-TFTs. In the first part, the methods called location-controlled vertical single grain-boundary (VSGB) low temperature poly silicon (LTPS) thin films transistors with bottom gate (BG) structures fabricated by excimer laser annealing were investigated. The mechanisms of VSGB-LTPS thin film were studied. A thick amorphous silicon region was formed in the corner due to the step structures of bottom gate which they served as the seeds for lateral grain growth during excimer laser irradiation. The laser energy density must be controlled to completely melt the thin region in the channel and partially melt the thick region near the corner. In addition, the lateral grain growth starting from channel edge could progress along the opposite direction toward the center of channel region. There was only one longitudinal boundary in the center of the channel. Thus, a large-grain polycrystalline silicon film was obtained which would lead to improved device performance. Various analyses were performed to investigate VSGB-LTPS thin films. From the analyses of scanning electron microscope (SEM), transmission electron microscope (TEM) and atomic force microscope (AFM), large longitudinal grains artificially grown measuring about 0.75μm were observed. Electrical characteristics of VSGB LTPS-TFTs were also studied. High-performance VSGB-LTPS-TFTs, which were fully compatible with the process flow of conventional bottom gate LTPS-TFTs, with field-effect mobility exceeding 250cm2/V-s have been fabricated without any hydrogenation treatment. Low GIDL effect and kink effect were also observed. The uniformity were also improved by this method. If twenty VSGB LTPS-TFTs devices were taken into discussion, the standard deviation of mobility was smaller than 30cm2/V*s and the standard deviation of Vth was smaller than 0.5V. Moreover, the VSGB-LTPS-TFTs could be fabricated with thinner gate oxide without any reliability issue such as lower breakdown field of gate oxide which was serious in conventional top-gate ones. Therefore, higher performance VSGB-LTPS-TFTs with larger driving current and better subthreshold swing could be easily produced by thinner gate oxide without additional structures or materials. Although VSGB-LTPS-TFTs exhibited high performance characteristics, asymmetrical electrical characteristics were also observed in VSGB-LTPS-TFTs due to the mis-aligned ion implantation. In the second part, we introduced the novel method called self-aligned location-controlled vertical single grain-boundary (VSGB) low temperature poly silicon (LTPS) thin films transistors with backside UV exposure. The simple process flows were also fully compatible with conventional bottom gate process. The amorphous gates could act as the masks of the lithography to stop the ultra violate light from the Hg light. From the OM and SEM images, the P.R. was self-aligned perfectly with the amorphous gate regions. Besides the advantages of VSGB-LTPS-TFTs, symmetrical electrical characteristics were also observed in SA-VSGB-LTPS-TFTs. The SA-VSGB-LTPS-TFTs exhibited better electrical characteristics than mis-aligned ones. SA-VSGB-LTPS-TFT with field effect mobility of about 192 cm2/V-s could be achieved while the mobility the counterpart was about only 17.76 cm2/V-s. The GIDL and kink effect were also reduced. Alghough VSGB-LTPS-TFTs shown high performance, SA-VSGB-LTPS-TFTs fabricated by this method were more suitable to the elements of the pixel switch devices. Unfortunatelly, there was still one high angle grain boundary in the channel of SA-VSGB-LTPS-TFTs. Therefore, a new continuous wave (CW) laser crystallization (CLC) to form directional lateral grain was proposed in the third part of the thesis. First, dopant activation by CW laser annealing was studied. It was found that dopant activation by CW laser annealing was a low-thermal budget and high-efficiency method. Low sheet resistance of 47 Ω/□ was observed. Second, we demonstrated the high performance n-type and p-type LTPS-TFTs fabricated by CLC method. According to previous reports, the grain boundaries were generally parallel to one another and to the scan direction of the laser beam by CLC methods. Therefore, high performance LTPS-TFTs without any high angle grain boundary could be fabricated and the mobilities were 192 cm2/V-s for n-type CLC-LTPS-TFTs and 92 cm2/V-s for p-type CLC-LTPS-TFTs, respectively. Moreover, the process flow was simple because the process flows were compatible with conventional top-gate LTPS-TFTs process. Additionally, due to the high scanning rate of CLC method, the throughput of CLC-LTPS-TFTs was improved. Hence, the CLC method was quite promising for the system on panel (SOP) application in the future.