增強靜電放電保護元件導通均勻度之設計

Abstract

大尺寸N型金氧半電晶體(NMOS)應用於靜電放電防護電路時，通常會以多指狀結構(multi-finger)來佈局，以降低元件所佔佈局面積。然而由於N型金氧半電晶體具有明顯的驟回崩潰特性，以及佈局上每根指狀N型寄生橫向雙載子電晶體之等效基極電阻之不同，造成多指狀結構N型金氧半電晶體在靜電放電轟擊下，並不會均勻的導通來排放靜電放電電流，而是集中於某些指狀N型金氧半電晶體。此不均勻導通的現象使得N型金氧半電晶體之靜電放電耐受度無法隨著元件尺寸增加而線性增加，造成靜電放電防護電路設計上的困難。 此篇論文主旨在改善多指狀結構N型金氧半電晶體之不均勻導通現象，並增強其靜電放電耐受度。設計宗旨為不需額外的觸發電路以及佈局面積，僅利用改變多指狀N型金氧半電晶體元件本身之電路接線，來改善不均勻導通之現象。第一個設計為自我基體觸發技術(self-substrate-triggered technique)，應用於閘極接地之N型金氧半電晶體。其原理為利用多指狀N型金氧半電晶體中，在靜電放電下最易先導通的中間之指狀N型金氧半電晶體元件來對所有指狀元件作基體觸發，以促進多指狀N型金氧半電晶體均勻導通。此設計已成功驗證於0.13微米互補式金氧半導體製程中，其靜電放電耐受度在相同元件尺寸下，比傳統的閘極接地N型金氧半電晶體提升了兩倍。第二個設計為等基體電位技術(equal-substrate-potential technique)，應用於串疊N型金氧半電晶體(stacked-NMOS)。其原理為利用佈局技巧，使每個指狀串疊N型金氧半電晶體寄生之橫向雙載子電晶體具有相同的基極電位，以促進元件導通均勻度。此設計驗證於0.18微米互補式金氧半導體製程，實驗結果顯示其導通電阻較傳統結構小，人體放電模式(Human-Body-Model, HBM)靜電放電耐受度較傳統串疊N型金氧半電晶體高，而機械放電模式(Machine-Model, MM)之靜電放電耐受度則沒有差別。 本論文之研究成果已發表於國際研討會論文，並投稿至國際期刊，已被接受。

To sustain the required ESD levels, the device size of NMOS used in ESD protection circuit is often designed with large device dimensions, which are often drawn with the multi-finger layout style to reduce the total occupied silicon area. However, because of the obvious snapback breakdown characteristic of NMOS transistor and the layout geometry effect on the distributed base resistance of each parasitic lateral bipolar transistor, multi-finger NMOS cannot be triggered on uniformly under ESD stress. The ESD current is only concentrated on some fingers. Therefore, the ESD robustness of multi-finger NMOS cannot be increased linearly with the increase of device size. The aim of this thesis is to improve the turn-on uniformity of multi-finger NMOS. Objective of the proposed designs are to solve the non-uniform turn-on issue through simple circuit wiring of the multi-finger NMOS itself, and without external triggering circuit and increase of layout area. The first proposal is self-substrate-triggered technique applied to gate-grounded NMOS (GGNMOS). The design concept is to utilize the current of the most easily turned-on center fingers to trigger the substrate of all the other fingers. This design has been successfully verified in a 0.13-um CMOS process, and the ESD robustness of self-substrate-triggered GGNMOS could be improve twice larger than that of traditional GGNMOS. The second proposal is equal-substrate-potential technique applied to stacked-NMOS devices, and the design is verified in a 0.18-um CMOS process. The design concept is to equalize the substrate-potential of each parasitic lateral BJT inherent in stacked-NMOS and thus improve the turn-on uniformity. The experimental results show that equal-substrate-potential stacked-NMOS has smaller turn-on resistance than traditional stacked NMOS. The HBM ESD level could be improved through this design, but the MM ESD level is the same as traditional stacked-NMOS. Contents of this thesis have already been published on an international conference, a local conference, and accepted by an international journal.