具奈米尺度之共平面複晶矽可電抹除程式化唯讀記憶體的研究

Abstract

平面式複晶矽薄膜電晶體之非揮發性記憶體單元可以在低溫下（600°C以下）製作，兩個薄膜電晶體的閘極互相連結之後構成浮動閘極，然而體積較大的薄膜電晶體的汲極和源極互相連接構成控制閘極。我們可以藉由此種結構大幅降低生產成本。利用奈米線在邊緣處的曲率半徑較小，在相同電壓下，有較大的電場之特性，製作出多通道奈米線的薄膜電晶體，可以有效的降低導通電壓(threshold voltage)，增加開關電流比(On/Off ratio)，較陡峭的次臨界導通斜率(subthreshold slope)，和更優良的元件驅動能力，其電性較一般標準結構的薄膜電晶體為好。在記憶體方面，由於奈米線通道之元件具有較優越與較穩定的電晶體特性，便針對一條通道且其寬度為1.6μm與奈米線通道且其每條寬度為155nm之元件的記憶體特性作比較，可以明顯發現奈米線結構具有較大的記憶窗，且有比較高的寫入/抹除效率，主要是由於奈米線之記憶體元件具有分立奈米線，使得閘極環跨於通道時，形成環繞式的三向閘極(tri-gate)，閘極擁有較佳的控制能力，且閘極與通道形成多處稜角，此處有較強的電場分佈，使得電子較易透過FN-tunneling通過穿隧氧化層而儲存於氮化矽層的缺陷能階內，造成起始電壓的改變而擁有記憶體的特性，此技術將有機會被利用在系統面板上。 在本論文中，主要在探討將記憶體元件製作在類似玻璃基板上的特性，我們將以此種結構為基礎，加入奈米線的結構，使用電漿修補缺陷，進而得到更好的操作效能。

Planar Twin Cell TFT of NVM memory can be fabricated under 600C degree，Gate connecting the two TFT becomes the floating gate。 The larger TFT connecting the drain and source becomes the control gate。Using this type of device structure， we can save huge cost。Nanowire has larger electric-field in the corner region at the same voltage. The Twin-TFT with multiple nanowire channels have superior electrical characteristic, such as lower threshold voltage, higher On/Off ratio, steeper subthreshold slope, and superior driving ability. The memory characteristic with nanowire has better performance than that one with single channel .The memory characteristic of standard Twin-TFT, channel width of the device is 1.6u m, was compared with the nanowires Twin-TFT, each channel width of the device is 155nm. The Twin-TFT with multiple nanowires structure (NW Twin -TFT). These characteristics are due to the larger electric field at the corner region and more number of corners. The NW Twin-TFTs can be treated as high performance devices and also as high program/erase efficiency nonvolatile memory under adequate voltage range operation. In this thesis, The fabrication of Twin-TFTs with nano-wire channels is quite easy and involves no additional processes. Such a Twin -TFT is there by highly promising for application in the future system-on-panel display applications. In this thesis ,we fabricate the memory devices on the TFT and use the nanowire trigate structure and plasma treatment to improve device performance