低溫複晶矽薄膜電晶體之遷移率與可靠度之研究

Abstract

在本論文中，首先，我們研究利用氮化矽層去覆蓋複晶矽薄膜電晶體的新式結構。我們發現與傳統複晶矽薄膜電晶體相較之下，有著氮化矽覆蓋層的複晶矽薄膜電晶體有較好的電特性。我們提高了導通電流及場效遷移率，這是因為氮化矽覆蓋層在通道中造成張力還有降低源極/汲極的串聯電阻。再者，氮化矽覆蓋層的複晶矽薄膜電晶體也抑制了扭曲效應 (Kink effect)，閘極引發汲極漏電(GIDL) , 還有改善了可靠度，這是因為此種新式結構薄膜電晶體可以降低橫向電場。 接著，我們進行有關P型通道之多重通道(multi-channel)複晶矽薄膜電晶體的研究。此種元件的電特性如導通電流，臨界電壓(threshold voltage)及次臨限擺幅(subthreshold swing) 會隨著通道條數變多而被改善，這是因為我們提高了有效的通道寬度和加強了閘極的控制能力。而元件的可靠度也會隨著通道條數增加而被改善，這是因為在多重通道結構下加強了閘極的控制能力。 最後，我們探討有關複晶矽薄膜電晶體生命週期(lifetime)的問題。發現到最糟的熱載子應力測試條件跟元件的通道長度有相關性。在短通道元件中，最糟的熱載子應力測試條件是閘極電壓等於臨界電壓而非傳統上閘極電壓等於二分之一汲極電壓。此外，導通電流退化的情形在高和位的汲極應力測試下的不同的現象。這是因為在薄膜電晶體中不僅碰撞游離(impact ionization)還有寄生雙極性接面電晶體效應(parasitic bipolar junction transistor effect)去造成元件的退化。我們亦發現當在粹取複晶矽薄膜電晶體之生命週期時與金屬氧化層場效電晶體有著不同的現象，在一大範圍的汲極電壓應力測試下有著兩種斜率的生命週期投射現象。

In this thesis, first, we studied the new structure of poly-Si TFTs with capping silicon nitride passivation layer. It was found that this device have better electrical characteristic than convention poly-Si TFTs. We enhanced electron mobility and on current due to local tensile strain in the channel and low source/drain series resistance. Moreover, the proposed poly-Si TFTs also suppressed kink effect, effect of gate induced drain leakage (GIDL) and improved reliability due to low horizontal electric field in this new structure of poly-Si TFTs. Then, p-channel poly-Si TFTs with multi-channel structure were studied. The device’s electrical characteristic such as on-current, threshold voltage, and subthreshold swing were improved with increasing the channel stripes due to the increasing effective channel width and enhancement of gate control capability. The reliability of proposed poly-Si TFTs were improved with increasing the stripes of channel. This is due to better gate control capability in multiple channel structure. Finally, we studied the lifetime issue of poly-Si TFTs. It was found that the worst-case of stress condition depend on device channel length. In short channel device, the worst-case of stress condition is under VG□Vth, not VG=1/2 VD. Moreover, Ion degradation under both high and low VD of stress conditions has different phenomena. This is due to not only impact ionization but also parasitic bipolar junction transistor effect to degradation poly-Si TFTs. Then, it is found that lifetime extraction of poly-Si TFTs is not the same with that of MOSFETs. There are dual slop lifetime projections in wide drain voltage.