矽鍺薄膜在不同氧化條件下之電性研究

Abstract

近年來，隨著元件尺寸縮小，增加載子遷移率已成為提升元件效能的趨勢之一，而電子及電洞遷移率皆高的矽鍺合金在此情況下也自然而然地被廣泛研究。藉由對矽鍺合金氧化，我們可以輕易提高鍺在矽鍺合金中的比例，進而造成更高的電子及電洞遷移率。在本實驗中，我們對矽鍺薄膜做了多種不同條件的氧化製程，並且製作成為傳統的金氧半場效電晶體(MOSFET)，藉由電性的量測，我們研究不同氧化條件對於矽鍺-金氧半場效電晶體的電特性影響。從實驗中我們發現，氧化溫度越高、時間越長、氧氣流量越大的元件，表現出較佳的電流特性；而在氧化速率的實驗中，氧化較慢的元件則有較低的漏電流。在文中，我們嘗試找出造成這些現象的可能原因，並且探討出最佳的氧化條件。

As channel length of metal-oxide-semiconductor field-effect transistors (MOSFETs) is deeply scaled down, enhancing the carrier mobility in the channel is desired for improving the performance of complementary MOS (CMOS) circuit. SiGe is a promising channel material because of its high electron and hole mobility. Higher Ge content in SiGe film makes higher mobility of both electrons and holes, and the oxidation process of SiGe is an easy way to achieve higher Ge content. In this study, various oxidation conditions were performed of SiGe film, and a conventional p-MOSFET was fabricated on it. I-V characteristics were measured to investigate the influence on electrical properties of the various oxidation conditions. It is found that the devices of higher oxidation temperature, longer oxidation time, and higher oxygen flow show better electrical performance. It is also found that devices under lower oxidation rate has lower leakage current and then induce higher On/Off ratio. Discussions of the results were made and the optimum condition of oxidation was therefore suggested.