適用於高解析度靜態影像與視訊應用之H.264/MPEG-4 AVC框內編解碼器設計

Abstract

近幾十年來，數位視訊科技已被廣泛地使用並成為生活中不可或缺的一部分。隨著數位訊號處理的發展，以及對較佳編碼效能的要求，H.264/AVC被認為是次世代的國際視訊編碼標準。和早期的標準相比，在強大的編碼技術下，新的視訊標準可以明顯地降低資料量但仍維持視訊品質。在這些技術中，空間性的框內編碼是具有高編碼效率的新工具。高品質的編碼效率使得框內編碼不但適用於單張畫面的視訊編碼，也適用於靜態影像壓縮，甚至可以和最新的影像編碼標準JPEG2000相比擬。然而，因為複雜的編碼技術，框內編碼的運算複雜度也比之前的標準高的多。因此，如何減少複雜度並設計一個高效能的框內編碼器或解碼器，而不會造成太多的效能衰減，是個重要的課題。在本篇論文中，我們提供一個框內編解碼器和一個快速框內編碼器的兩個硬體實現來解決此問題。 首先，我們提出一個演算法層次和系統層次皆最佳化的基本規格框內編解碼器架構。為了在近似相同的視訊品質下減少硬體成本和增加處理速度，以硬體為目的的演算法移除了佔空間的平面預測並以更準確的代價函數來加強模式決定過程。在架構設計方面，除了快速的模組實現外，由巨圖塊層次的管線化型式和三個排程技術來安排編碼過程，以避免閒置的週期並改善資料生產量。整個編解碼器設計最後可以分別在117MHz時脈下支援高解析度1280x720尺寸30fps的即時視訊編碼，以及在58MHz下支援高解析度1920x1080尺寸的視訊解碼。 另一個成果，是具有快速模式決定演算法和可變像素平行化技術，針對低功率問題設計的基本規格框內編碼器。經由提出修改後的三步驟演算法流程，模式決定的過程可以被縮短。此外，可變像素平行化的資料路徑也可以有效地節省約一半處理週期，並導致較低的頻率需求。在交錯排程的技術和三個低功率考量的策略下，新設計比之前的設計有較小的晶片面積，並只需61MHz即可支援高畫質1280x720尺寸30fps的即時視訊編碼。 簡而言之，我們對於H.264/AVC框內編碼的貢獻可以分成兩個部分。一個貢獻是框內編解碼器，在最小的硬體成本和處理速度的改進下，整合了編碼和解碼的過程。另一個貢獻是快速框內編碼器，特性包括了降低運算複雜度，壓制頻率需求，以及對於低功率課題的策略。

For the recent decodes, digital video technology has been popularly used and become a necessary part in our daily life. With the development of digital signal processing and demand of better coding performance, H.264/AVC is regarded as the international video coding standard for the next generation. The new standard can achieve significant bitrate reduction compared to earlier standards but still maintains the video quality with its powerful coding techniques. In these techniques, the spatial intra coding is a newly proposed coding tool with high coding efficiency. The high-quality coding efficiency makes intra coding not only suitable for single-picture video coding but also for still image compression, and even competitve with the latest image coding standard like JPEG2000. However, due to the complicated coding techniques, computational complexity of intra coding is much higher than previous standards as well. Thus, how to reduce the complexity and to design a high-efficient intra coder or decoder without much performace degradation is an important issue. In this thesis, we contribute two hardware implementation of an intra frame codec and a fast intra frame encoder to solve this question. We first propose a baseline intra frame codec architecture with both algorithm-level and system-level optimization. To reduce hardware cost and increase processing speed while providing nearly the same video quality, the hardware-oriented algorithm removes the area-costly plane prediction and enhances the mode decision process with more accurate cost function. In the architecture design, in addition to fast module implementation the process is arranged by the macroblock-level pipelining style together with three scheduling techniques to avoid idle cycles and improve data throughput. The whole codec design finally can support high definition 1280x720 size 30fps real-time video coding at 30fps when clocked at 117MHz and high definition 1920x1080 size decoding at 58MHz respectively. The other work is the baseline intra frame encoder targeted on low-power issues with techniques like fast mode decision algorithm and vairable-pixel parallelism. The mode decision process is shortened by the proposed modified three-step algorithm. Besides, the vairable-pixel parallel datapath can also effectively save almost half of processing cycles and lead to lower frequency requirement. With the technique of interlaced scheduling and three strategies for low-power consideration, the new design has smaller chip area relative to previous designs and can support high definition 1280x720 size 30fps real-time video coding at only 61MHz. In brief, our contributions to H.264/AVC intra coding can be divided into two parts. One contibution is the intra frame codec, which integrates both encoding and decoding processes with minor hardware cost and improvement of processing speed. The other contribution is the fast intra frame encoder, with features of reduction of computational complexity, suppression of frequency requirement, and strategies for low-power issues.