應用於IPv6位址搜尋之高能源效應內容可定址記憶體電路設計

Abstract

本論文利用平行交錯式比對與基於無關項的低功率技術，提出了一個全新的高速低功率抗雜訊的三元內容可定址記憶體。利用高度的平行化搜尋，butterfly結構使得比較線上的搜尋延遲得以降低。利用IPv6無關項的特性，可以阻斷比較線上預先充電電路的路徑。並利用搜尋時因無關項造成比較符合時與搜循線上的資料無關的特性，可以阻斷階層式搜尋線之資料傳遞。一個高速低功率256行×128位元之三元內容可定址記憶體亦被提出，利用TSMC 0.13μm CMOS 技術來實現電路設計與佈局。根據模擬結果顯示，此新的三元內容可定址記憶體在最大操作頻率500Mhz可以達到0.22fJ/bit/search的能源表現與0.71ns的搜尋時間。

The new high speed, low-power and noise-tolerant ternary content-addressable memories (TCAMs) using butterfly match-line scheme and don’t care based low power technique are realized in this thesis. Butterfly match-line scheme reduces search delay by high parallel search. Furthermore, for IPv6 addressing lookup application, butterfly match-line scheme reduces switching activity also. By use of XOR-based conditional keepers, power consumption and search delay further reduced. The potential charge-sharing problem in the AND match-line could be solved also. Don’t-care based low power technique takes the advantage of application future of TCAM. Don’t-care based power-gating eliminate unnecessary precharege. Don’t-care based hierarchical search-line scheme decrease switching capacitance. A 256-word x 128-bit energy-efficient ternary CAM is also proposed and simulations and layout are implemented in TSMC 0.13μm CMOS technology. Simulation results show that 0.29fJ/bit/search energy performance and 0.65ns search time operate in maximum frequency 500Hhz.