適用於H.264 HDTV 解碼器之有效率動作補償記憶體架構

Abstract

在視訊解碼的領域中，H.264/AVC是由ITU-T/ISO所提出新的視訊標準。由於H.264/AVC高壓縮率以及視訊品質的提昇，使得H.264/AVC是目前最受歡迎的標準。由於數位電視的風行，而主要著重於視訊資料品質的H.264 Main Profile規格也漸漸被重視。因此對於高畫面的解析度上高速解碼及畫面品質的提昇是最重要的挑戰。而視訊解碼標準中，動作補償（Motion Compensation）架構一向是最重要的部份也是整個系統的核心所在。在Main Profile規格裡面為了加強視訊品質而加入新的功能，例如：雙向預測、加權預測、直接預測編碼。在本論文中，針對支援Main Profile規格設計動態補償架構以符合高速的規格以及高品質的解析度。對於H.264解碼器中我們提出了有效的動作補償模組來提昇速度。此外，對於動作補償中小數點內插器的架構，我們提出了2D擴充行列式方法（Extended-2D Column Major Approach）以及新的架構來有效率的降低解碼器所需要的頻寬以及降低整個小數點內插器的複雜度。新的架構也合併了兩種block 格式(Luma 以及 Chroma) 的小數點內插器，使得這兩種格式都可以使用相同的架構。我們所提出的小數點內插器架構比起其他的架構可以有效降低複雜度20%，而且所需要的頻寬可以降低約50%~60%來提昇動作補償的速度。 此外，動作補償系統需要從外部記憶體SDRAM存取大量資料，因此對於外部記憶體的存取是影響整個解碼器系統的關鍵。增加外部BUS上的頻寬將會提昇動作補償的效能以及支援更大畫面的解析度。一般的記憶體控制器並沒有對於多媒體方面的各個模組作設計。在本篇論文中將會對於存取外部記憶體提出適用於HDTV H.264解碼器有效率的記憶體控制器。將可以支援解碼器中的模組對於外部存取的需求，例如：動態補償及去方塊效應濾波器(De-blocking filter)。實現彈性、高速的動態補償系統架構設計。另一方面，我們所提出的記憶體控制器可以支援H.264 多重參考圖片的技術，並且可以有效率的利用單一記憶體即可存取所需要的參考圖片資料。我們所提出的記憶體架構可以提昇BUS 利用率(Bus Utilization) 至90%以上。透過我們所提出的動作補償架構以及記憶體架構，整個系統對於記憶體讀取的頻寬將會改善40% ~ 50％。最後，我們解碼器系統Throughput 在高位元率的壓縮比下可以也可以符合標準所訂定的HDTV規格。

H.264/AVC is the new video coding standard of ITU-T Video Coding Experts Group (VCEG) and the ISO/IEC Moving Picture Experts Group (MEPG). H.264 is most popular video standard due to high compress rate and better quality. In particular, the baseline profile of H.264/AVC has been accomplished progressively. In recently year, digital TV is widely adopted so that H.264’s Main Profile focus on quality of video will be attended gradually. Therefore, the improvement of resolution and quality for large frame will become important issue. Motion compensation always is important module and kernel of system in video standard. For enhancing quality of video, H.264’s main profile adopts new features such as Bi-prediction, weighted prediction and direct mode coding. In this thesis, a bandwidth-efficient motion compensation system is proposed for high definition resolution supported by main profile in H.264/AVC. Presently, we provide a novel structure of motion compensation system in main profile to improve system throughput. Furthermore, we propose Combined Luma/Chroma interpolator architecture in motion compensation and a novel data-reuse technique: Ectended-2D Column Major Approach. Both Luma and Chroma MB can be interpolated by combined Luma/Chroma interpolator. A combined Luma/Chroma interpolator is proposed in order to save area, which achieves approximately 44% cost reduction. Additionally, an Extend-2D column major approach is presented, which improves 50% ~ 60% required bandwidth within decoder. The video decoder should deal with large amount of data from external memory due to a real-time high-quality decoding demand. Therefore, both limited access time and bandwidth of memory access on BUS is bottleneck of entire video decoder. However, general memory controller may be not design for multimedia applications. In this thesis, the bandwidth-efficient memory controller architecture is proposed for H.264 decoder to increase limited bandwidth over external bus. The memory controller can support all module of H.264 decoder such as motion compensation and de-blocking filter, etc. Besides, the multiple reference pictures technique can be supported by our proposed memory controller, and can employ unique memory to store all required data for video decoder. About simulation results, the bus utilization can be improved up to 90% for our proposed memory controller. The bandwidth of memory access may be improved to 50% ~ 60% for entire video decoder adopting our proposed bandwidth-efficient motion compensation memory organization. Finally, the system throughput that is proposed by our proposed architecture can meet with specification with HDTV standard at high bit-rate.