標題: Carry Estimation of Truncated-Width Multiplier for FFT Application截斷乘法器之進位估計與其快速傅立葉轉換應用 作者: 趙祐徵張錫嘉電子研究所 關鍵字: 截斷乘法器;固定乘法器;進位估算;truncated-width multiplier;fixed-width multiplier;carry estimation 公開日期: 2006 摘要: 在本論文，我們提供了一個用統計方式來分析截斷乘法器補償。在截斷乘法器中，被截去部分的誤差可以用簡單的進位公式來補償。本論文對Baugh-Wooley以及Booth乘法器各提出了三種不同的補償方式。藉由以我們所提出的這些補償方式，與使用direct-truncate方法的 Baugh-Wooley以及Booth乘法器相比較之下，各減少了約85%以及80%的誤差。此外，我們將此補償方法應用在64點FFT的乘法器裡面，可以得到與post-truncate相近的SQNR(Signal to Quantization Noise Ratio)。當應用於2048點FFT時，我們所提出的方法可以大約降低約4.7%的面積而其SQNR值亦不會與post-truncate有太大的差異。This thesis provides a statistical analysis for truncated-width multiplier which receives two n-bit inputs and truncates n-bit output. The truncated parts which produce carry-in can be replaced by carry estimation methods. In order to reduce the truncation error, different compensation methods are provided for different bit-width. This thesis discusses Baugh-Wooley and Booth multiplier and provides three types of compensation method for these two multipliers. According to the simulation result, about 85% and 80% error of the direct-truncation Baugh-Wooley and Booth multipliers can be reduced. For the 64-point FFT case, the software simulation shows similar performance while comparing to post-truncate method. For the hardware of 2048-point FFT, our method can reduce about 4.7% gate count while comparing to post-truncate method without performance loss. URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009311684http://hdl.handle.net/11536/78155 Appears in Collections: Thesis

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