在晶片與封裝共同設計時對於核心區塊與輸入輸出緩衝器擺置的方法

Abstract

隨著矽製程的發展，我們能夠在單一個晶片中放置越來越多的電路。這代表了越進步的設計將需要越多的輸入輸出訊號。覆晶封裝方式是IBM在1960年代所發展出來的，它比典型的周邊打線接合方式在輸出入訊號上能提供更多的個數，覆晶設計其中一個最重要的特性就是輸出入緩衝器可以像核心電路一樣放在晶片內的任何一個地方。在這邊論文裡，我們發展了一個在覆晶設計時，核心區塊與輸出入緩衝器擺置的演算法並且同時考量接線長度、訊號歪斜與電源完整性.

As silicon technology scales, we can integrate more and more circuits on a single chip,which means more I/Os are needed in modern designs. The flip-chip packaging was developed by IBM in 1960's. It is better than the typical peripheral wire-bond design in the increase in I/O count. One of the most important characteristics of flip-chip designs is that the input and output buffers could be placed anywhere inside a chip, like core cells. In this thesis, we develop an block and I/O buffer placement algorithm in wire length and signal skew optimization and power integrity concerning for flip-chip design.