自發性比例式記憶體細胞非線性網路之設計

Abstract

在圖形辨識的領域中，聯想式記憶體是一種相當熱門的辨識方法，它能將含有雜訊的圖形恢復成完美無雜訊的圖形，而比例式記憶細胞非線性網路已被證實可以作為一種聯想式記憶的實現方法。而目前比例式記憶體非線性網路所面臨的挑戰即是如何提升其在高雜訊的環境下的辨識率。 本論文的主旨在於闡述自發性比例式記憶體細胞非線性網路（Autonomous Ratio-Memory Cellular Nonlinear Network，簡稱ARMCNN）架構之分析與設計及其在聯想式記憶及圖像辨識上之應用。所謂的自發性是指在辨識階段，帶有雜訊的輸入訊號將在各個細胞存成初始電壓，而非一固定的輸入電壓。此外，本設計也具有免衰減操作即可得到所需比例鍵值之優點。在圖形學習階段，過去的比例式記憶細胞非線性網路（Ratio-Memory Cellular Neural Network，簡稱RMCNN）比例鍵值產生方式是將絕對鍵值（absolute weight）與細胞鄰近四邊的絕對鍵值平均值作比較，如果大於平均值，則此鍵值將被保留，反之則忽略此鍵值。而新提出的ARMCNN，是將細胞相鄰四邊的絕對鍵值改為只保留最大的絕對鍵值。模擬結果證明自發性比例式記憶細胞非線性網路相較於具有較高的辨識率。 論文中除了以Matlab和C語言模擬自發性比例式記憶細胞非線性網路架構（ARMCNN）及其在聯想式記憶和圖像辨識上之應用外，並實際以TSMC 0.35um 2P4M Mixed-Signal製程設計了一解析度為9x9的ARMCNN網路，並實現之且加以量測。本設計的單位面積在相同製程下，縮小為前一版設計─免衰減操作之RMCNN的0.28倍大（從4.56mm x 3.90mm縮小到2.24mm x 2.24mm）。 量測中所學習的三個圖形（一、二、四）皆可成功的辨識，而辨識中的一些瑕疵， 也將在論文中進行探討。並從新設計電路，在Hspice模擬驗證新電路確實可以改善此缺陷。

The associative memory is of significant attention in the field of pattern recognition and recovery. It is proven that the cellular nonlinear network with the aid of ratio memory (RMCNN) can be used to implement as a kind of associative memory. However, there are still some imperfections that require further improvement for the existing RMCNN system. For example, the pattern recognition rate of RMCNN drops quickly as the environmental noise level raises. Moreover, the die area of the existing chip is too large (4.56mm x 3.90mm), which might suffer from the impact of process variation more seriously. Therefore, the chip area reduction and optimization are necessary. A new type of CNN associative memory called the Autonomous Ratio-Memory Cellular Nonlinear Network (ARMCNN) is proposed and analyzed. In the proposed ARMCNN, there is no elapsed operation to perform weight enhancement as well. During recognition period, the noisy input patterns are sent into cells as initial cell state voltages, which in comparison with constantly injecting the noisy input patterns, yields a better recognition rate in simulation. During pattern learning period, the ratio weight is original generated by comparing the four neighboring absolute weights with their mean value. The absolute weights that are bigger than the mean value will remain. However, in ARMCNN, only the strongest absolute weights will stay (might be more than one). Furthermore, the proposed ARMCNN inherits the features of RMCNN such as, feature enhancement effect and no elapsed operation (EO). The ratio weights are generated directly after pattern learned. In this thesis, the circuit of ARMCNN w/o EO is designed and a 9x9 ARMCNN is implemented using TSMC 0.35um 2P4M mixed-signal process. The die area, as compared with the previous chip – RMCNN w/o elapsed operation, shrinks from 4.56mm x 3.90mm to 2.24mm x 2.24mm. It’s only 0.28 times as large as the previous chip under the same technology process, which greatly reduces the impact of process variation. The experimental results of recognizing all three patterns are successful. However, some imperfections of pattern recovery still exist and will be discussed later in this thesis. The circuit is redesigned to correct these imperfections.