完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | 林建宏 | en_US |
dc.contributor.author | Jian-Hong Lin | en_US |
dc.contributor.author | 張國明 | en_US |
dc.contributor.author | Kow-Ming Chang | en_US |
dc.date.accessioned | 2014-12-12T02:52:18Z | - |
dc.date.available | 2014-12-12T02:52:18Z | - |
dc.date.issued | 2007 | en_US |
dc.identifier.uri | http://140.113.39.130/cdrfb3/record/nctu/#GT009311807 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/78172 | - |
dc.description.abstract | 隨著元件尺寸的微縮,為了確保元件的良好表現,有許多新的材料被導入元件的製程。然而這些新材料的熱穩定性並不十分一致,導致製程整合的複雜化。有些在其他特性表現不錯的材料也因此不被採用。究其原因,離子植入後的高溫活化是製程整合上的主要瓶頸。離子佈植進入矽合金法是一種能在低溫下活化載子的方法。本篇研究主要著重利用離子佈植進入鎳矽合金法在低溫活化形成的接面特性的相關研究。 第一部分,我們想研究低溫活化的可能機制。首先我們藉由製作金屬半導體二極體的測試結構,量測在不同的活化條件下,載子活化的情形,確認了低溫活化下,在金屬和半導體接面的載子具有相當高的活化程度。藉由此部分的研究成果,讓我們可以接著去設計實驗來觀察並且分析利用此離子佈植入鎳矽合金法在低溫活化形成的PN接面。接著,我們分析了深淺兩種不同的佈植深度所形成的接面行為的變化差異,提出了三個離子佈植入鎳矽合金法的在低溫活下可能的活化機制,包含了金屬促發的再結晶,固態長晶再結晶,以及基材本身活化。 第二部分,我們想對藉由離子佈植入鎳矽合金法形成之接面特性做進一步的了解。首先,根據第一部分的研究結果,為了研究very shallow junction,我們降低了植入載子的濃度,觀察並且記錄了相關的電特性且與先前的高離子佈植的元件比較。接著,導入了第三段的熱製程溫度,觀察了元件的熱穩定度特性。藉由交叉比對實驗結果,我們對於該元件的製作和量測方法提出了我們的觀點。 | zh_TW |
dc.description.abstract | Many new materials have been introduced to ensure the device with high quality as their physical lengths are scaled down. However, some materials may not have good thermal reliabilities, hence making the process integration more and more complex. As the result, some materials may have good characteristics in many aspects, but they couldn’t be adapted to the fabrication process. The highest temperature appears in device fabrication is the dopant activation step after implantation and this step dominates the thermal reliability requirement for all materials. Implant into silicide method is one possible method to activate dopant at low temperature. And in this study, we focus on the characteristics of junction formed at low activation temperature by using implant into nickel silicide method. In Part I, we want to clarify the possible mechanism that active the dopant at low temperature. At first, we fabricated Metal Semiconductor diode (MS diode) test structure at different activation conditions. By measuring and analyzing the dopant activation abilities of MS diodes formed at different conditions, we confirm the factor that even at low temperature activation, the dopant at the MS interface also has high activation ability. Based on this result, we can go a step further to design an experiment to observe and analyze behaviors of junction formed by the implant into nickel silicide method. Then, by comparing different behaviors of junctions (deeper and shallow) with two implantation energies, we proposed three possible corresponding dopant activation mechanisms at low temperature to the implant into nickel silicide method. Which includes doping activation at metal assisted re-crystallization region, solid phase regrowth region and bulk activation region. In part II, we want to understand characteristics of the junction formed by IIS method further. By the experimental results in Part I, for very shallow junction fabrication, we lowered the implantation dosages and then we record relative electrical properties and also compare results to the heavily implanted samples. Then, an added thermal treatment is adapted to explore the thermal reliability issue of these devices. By cross comparing experimental results, we proposed our viewpoints of the IIS method. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | 離子植入鎳矽合金 | zh_TW |
dc.subject | 固相磊晶再成長 | zh_TW |
dc.subject | 離子接面非等向擴散 | zh_TW |
dc.subject | Implant into silicide | en_US |
dc.subject | Solid Phase Epitaxial Regrowth | en_US |
dc.subject | Dopant Segregation | en_US |
dc.title | 藉由離子佈植進入矽合金法在低溫活化下形成的接面研究 | zh_TW |
dc.title | A Study of Low Temperature Activated Junction Formed byImplant Into Silicide Method | en_US |
dc.type | Thesis | en_US |
dc.contributor.department | 電子研究所 | zh_TW |
顯示於類別: | 畢業論文 |