應變金氧半場效電晶體機械應力萃取與其相關物理模型建立之研究

Abstract

近來，金氧半場效電晶體中機械應力已引起大量的注意，特別是在電性(如：載子遷移率、驅動能力及漏電流)及物理現象(如：摻雜擴散及介電層缺陷)的改變。因此本論文將會展示如何評估元件中各處應力量值。接著，在處理上述議題時，相對應的理論模型或分析將可被建立基於提出的方法之上。 首先，針對具有1.27奈米閘極氧化層且經由佈局技巧所產生的通道方向應力的n型金氧半場效電晶體進行導帶電子直接穿隧電流量測。藉由已知製程參數及已發表形變位能常數，計算不同電壓下閘極電流變化百分比可以得到通道平均應力量值。為驗證此法的精確性，在相同元件上進行載子遷移率的量測。所產出的壓阻係數與發表的數值高度相符。而佈局技巧也同時成功藉由經驗公式所檢驗。 其次，利用不同的通道寬度，量測在具有壓縮應力淺溝槽絕緣層下的閘極穿隧電流。每單位通道寬度之閘極電流隨著寬度下降，呈現增加的趨勢。在這窄縮的方向，兩個基本的效應須同時考慮：一為在淺溝槽絕緣層邊緣的寬度修正，另一為增長的通道應力。為了區別此兩因素，一個新的解析寬度依存閘極穿隧電流模型已被成功的建立及使用。而所得到的寬度修正效應在較為窄小的元件中，相較應力具有壓倒性的重要。然而，對於較寬的元件，此兩效應的影響是相當的。萃取出之寬度修正量值及應力大小可以直接重現汲極電流變化。特別的是，寬度修正與應力對閘極電流的影響趨勢相同，但對汲極電流影響相反。 再者，不同閘極邊緣至淺溝槽絕緣層寬度下元件的次臨界電流被量測並轉換成源極/汲極延伸區應力值。此萃取出的局部應力大小與在相同元件上，藉由閘極穿隧電流及載子遷移率所評估的通道應力趨勢相符。閘極邊緣穿隧電流可以直接導出閘極與延伸區重疊長度的量值。特別是，在壓縮應力下造成摻雜擴散縮短的長度及應變引發的活化能量值與製程模擬結果相符。亦成功建立一個以物理導向的解析模型，將側向擴散長度表為延伸區應力的函式。 最後，在p型通道金氧半場效電晶體上的低頻雜訊量測得出：隨淺溝槽絕緣層拉伸應力在寬度方向的增加將會導致氧化層界面缺陷的減少。在此，兩種可能的物理緣由被提出：在氧化過程中，(一)較為鬆弛的介面應變；以及(二)單位面積下較為減少的過量矽原子。

Recently, mechanical stress in MOSFETs has gained much attention due to significant changes in electrical performance (mobility, drive capability, leakage etc.) and process issues (dopant diffusion, gate oxide integrity etc.). Therefore, this dissertation is aimed at demonstrating how to measure stress quantities in each part of the devices and address the induced changes. Based on the proposed methods, the underlying physical framework can be established while meeting the above issues. We first measure the conduction-band electron direct tunneling current through 1.27-nm gate oxide of n-MOSFETs that undergo longitudinal stress via a layout technique. With known process parameters and published deformation potential constants as input, fitting of the measured direct tunneling current versus gate voltage leads to channel stress. To examine the accuracy of the method, a link with the mobility measurement on the same device is conducted. The resulting piezoresistance coefficient is shown to be in good agreement with literature values. The layout technique used is validated as well. Then, gate direct tunneling current under STI compressive stress is measured in a wide range of the drawn gate width W (= 0.11, 0.24, 0.6, 1.0 and 10 □m). The apparent gate current per unit width exhibits an increasing trend with decreasing W. In this narrowing direction, two fundamentally different effects are encountered: One of the delta width (□W) near the STI edge and one of the enhanced STI stress in the channel. To distinguish between the two effects, a new analytical width-dependent direct tunneling model is developed and applied. Reasonable agreement with data is achieved. The resulting delta width effect is found to dominate over the stress effect especially in the narrow devices, while for the wide ones, they will be comparable. The extracted □W and the underlying channel stress (with the uncertainties identified) straightforwardly produce a good fitting of the drain current variation counterpart. Specifically, it is justified that the delta width and STI stress are co-operative in constituting gate current variation but both have opposite effects on the drain current one. Third, drain subthreshold current is measured as a function of the gate edge to STI spacing and is transformed into the source/drain extension corner stress. The extracted local stress is quantitatively reasonable with those of the channel as created by the gate direct tunneling measurement in inversion, and the mobility measurement. In addition, its dependencies on the gate edge to STI spacing confirm the validity of the layout technique in controlling the stress. The gate edge direct tunneling (EDT) measurement in accumulation straightforwardly leads to the quantified gate-to-source/drain-extension overlap length. Particularly, a retarded diffusion length and the resulting strain-induced activation energy both are in satisfactory agreement with those of the process simulation. A physically oriented analytic model is therefore reached, expressing the lateral diffusion length as a function of the corner stress. Finally, low-frequency noise measurement on p-channel MOSFETs yields the density of the gate-oxide interface states, exhibiting a decreasing trend with increasing STI tensile stress in the channel width direction. Two plausible physical origins of the interface-state density suppression in narrow devices are proposed: relaxed interface strain and reduced excess silicon per unit area during the thermal oxidation.