具有低電壓以及良好電荷儲存能力之金屬-氧化層-氮化層-氧化層-矽結構非揮發性記憶體之研究

Abstract

在過去十年，由於可攜式電子產品市場的興起，例如手機和數位相機。低功耗以及低成本的記憶體元件已經吸引越來越多的注意，由於這些記憶體元件需擁有至少十年的資料儲存能力，因此非揮發性記憶體的地位日趨重要。 根據ITRS技術藍圖，浮停閘(floating-gate)非揮發性記憶體的關鍵技術在於穿遂氧化層的微縮，因為壓力所引起的漏電流(SILC)會造成儲存資料經由單一的缺陷而流失，此問題會在很薄的穿遂氧化層下愈顯嚴重，對於新興的單晶片系統(SoC)積體電路設計來說，由於非揮發性記憶體的編碼電壓必須和低電壓的邏輯電路相容，因此更是一項嚴峻的挑戰。近年來，基於電荷儲存原理所形成的多晶矽或金屬閘極-氧化矽-氮化矽-氧化矽-矽(SONOS/MONOS)記憶體元件和浮停閘記憶體元件相比，具有較低編碼電壓，較小單元尺寸以及較佳耐用度的優點，因此受到很大的關注。在SONOS/MONOS元件中，電荷是儲存於分離性的捕陷區而非浮停閘的連續性，僅有靠近缺陷附近的電荷會流失因此對SILC有更好的抵抗能力，另外穿遂氧化層也能更有效的微縮。然而，抹除速度以及資料儲存能力仍然是SONOS/MONO元件取代浮停閘元件的主要挑戰。 在此論文中，我們使用全新的高含氮量氮氧化鉿材料作為MONOS元件的捕陷層，此元件具有低的操作電壓，快的速度以及良好的電荷儲存能力。在快速(100毫秒)和低電壓(9伏)的操作條件之下，可得到2.8伏的記憶視窗;在85oC 和125oC環境下由外插法所得的十年資料儲存能力，其記憶視窗仍有1.8伏和1.5伏，由於我們調整高含氮量氮氧化鉿的捕陷能階深入至靠近矽中間能帶的禁止能帶中，才能在僅2.9奈米穿遂氧化層的MONOS元件中，擁有如此突出的資料儲存能力。為了進一步提升高溫下的資料儲存能力，我們提出了一種具有雙重量子井結構的MONOS元件，在快速(100毫秒)和低電壓(9伏)的操作條件之下，可得到3.2伏的記憶視窗，在150oC的環境下，其十年的資料儲存能力，仍然可維持在2.7伏，僅百分之二十五的視窗衰減，主要歸功於雙重量子井將被捕陷的載子侷限在高含氮量氮氧化鉿材料之中。以上兩種MONOS元件，只要設計一簡單的電路將記憶體元件之操作電壓減少一半便可以達到單一片系統的應用。

In the past decade, memory chips with low power consumption and low cost have attracted more and more attention due to the booming market of portable electronic devices such as cellular phones and digital cameras. These applications require the memory to have ten years data retention time, so that the nonvolatile memory device has become indispensable. According to ITRS roadmap, the key issue for floating-gate nonvolatile semiconductor memory (NVM) is the scaling of the tunneling oxide because the stress-induced leakage current (SILC), which can discharge the whole floating-gate memory with even one single defect, becomes a severe problem at very thin tunneling oxide thickness. This scaling issue is a formidable challenge especially for the emerging system-on-chip (SoC) integrated circuit designs in which programming voltage must be scaled for the NVM to be compatible with the low voltage logic circuit. Recently, silicon/metal-oxide-nitride-oxide-silicon (SONOS/MONOS) charge trapping based NVM has received considerable interest due to its advantage of lower programming voltage, smaller cell size and better endurance over the floating-gate devices. In SONOS devices charges are stored in discrete traps instead of continuous floating gate. As a result, such devices are more robust to SILC since only charges near the defect site can be discharged and the tunneling oxide layer can be scaled more aggressively than floating-gate devices. However, retention and erase speed remain as the major challenges for SONOS/MONOS devices to replace floating-gate devices. In this dissertation, we proposed a low voltage, high speed and good data retention MONOS memory device by using a high-k Hf0.3N0.2O0.5 trapping layer. At very fast 100 us and low +/- 9 V P/E, good memory device integrity of 2.8 V initial memory window and large ten-year extrapolated retention of 1.8 V at 85oC or 1.5 V at 125oC are obtained in SiO2/Hf0.3N0.2O0.5/HfLaON/TaN MONOS device. Such excellent 85~125oC retention with small decay rate, at only 2.9 nm thin tunnel SiO2, is possible by tuning Hf0.3N0.2O0.5 trap energy deep into Si forbidden bandgap close to midgap. To address the high temperature retention issue, we further provide the [TaN-Ir3Si]-[HfAlO-LaAlO3]-Hf0.3N0.2O0.5-[HfAlO-SiO2]-Si device. At 150oC under very fast 100 us low +/- 9 V program/erase, this device shows good memory device integrity of a 3.2 V initial memory window and 2.7 V ten-year extrapolated retention. This only 25% retention decay at 150oC was achieved by double quantum-barriers confining the deep-trapping-energy Hf0.3O0.5N0.2 well. Both above devices are useful for embedded SoC under a single 5 V voltage source by using a simple voltage inverter circuit.