高效能雙核心H.264編碼器之實現

Abstract

本論文提出一個具有雙核心特性的H.264編碼器。此編碼器在演算法層次上，對於程式執行的流程以及資料的存取，都做了徹底的改善和最佳化。我們在壓縮流程上，減少程式的分支，將壓縮過程中的判斷式減少，使得編譯器能發揮最好的效能去編譯程式。在記憶體使用方面，設計了有效的處理流程，讓ARM和DSP之間能分工平行處理目前的資料。使用雙核心架構的編碼器，可以讓DSP核心全力處理壓縮的運算部份，ARM核心負責資料流的輸出輸入以及週邊裝置的控制。此種架構除了提昇效能之外，更能最佳化處理器的使用方式。本論文提出的H.264編碼器，經由ARM讀取儲存裝置或者是週邊裝置裡的原始影像，將資料搬移到DSP去進行H.264的編碼。處理之後的結果，會由ARM端負責包裝成可以播放的影片檔案輸出。在實驗平台OMAP5912上執行的表現，對於品質和速度之間取得了平衡。利用平台的特性，此解碼器可應用在網路視訊傳輸或者是本機端錄影機。所提出之解碼器架構和最佳化方法，更能移植到不同的平台上，增加其應用方式。

In this thesis, a dual-core based and highly optimized H.264 encoder is presented. A major benefit of using a DSP-ARM dual-core processor is that it is possible to integrate system control functionalities with the H.264 encoding on a single chip. However, more benefits of significance can be obtained if DSP and ARM cores are programmed to execute signal processing jobs in parallel. The developed H.264 encoding system consists of a video compression processing part and a system control part. In the video compression processing part, the encoded data is encoded via H.264 encoding algorithm and converted to a playable file such as MKV files. The system control part is in charge of managing the encoded data files and transferring them from the storage to video compression processing part. The proposed encoder achieves balance between quality and speed. With OMAP5912, the implementation is well suited for videophones, and network streaming applications. The DSP core can perform encoding while the other can process network message as well as storing the encoded H.264 bitstream in the local host. The optimization techniques presented can be effectively used for other programmable processors with similar architectures and instruction sets.