連續時間和差類比數位轉換器之實作考量分析

Abstract

本篇論文為討論在設計Continuous-Time Sigma-Delta Modulator(CT SDM)的過程中，如何在系統模擬上考慮其非理想效應以及在電路上實現的方法，並將兩者之間的結果互相比對。在介紹Sigma-Delta Modulator的基本理論後，經由DT-CT係數的轉換得到適用於CT SDM的係數，接著從參考現有的文獻以及模擬過程中的發現，建立有限增益頻寬(Finite gain bandwidth)、回授路徑額外時間延遲(Excess loop delay)、時鐘抖動(Clock jitter)、RC時間常數變動(RC time- constant variation)、係數值變動(Coefficients variation)、電容電阻不匹配(R、C mismatches)等非理想效應相關的模擬環境。並對於不同架構的差異性：(1)二階及三階的CT SDM (2)回授路徑上不同時間延遲的架構(unit-delay和half-delay) (3)用於CRFF架構的加法電路 (4)前饋(Feed-forward)與回授(Feed-back)架構的比較(CRFF和CRFB)等做模擬與分析探討。論文中使用MATLAB Simulink做系統上的模擬，在電路上則以台積電TSMC 0.18μm Mixed Signal 1P6M 1.8V製程設計實現。最後，在模擬上所達到的規格為250 kHz, 4mW, 83dB SNDR 3rd-order CRFF CT SDM。

Abstract This thesis discusses the methods to simulate non-idealities in behavioral environment and practical realization in circuits when designing a continuous-time sigma-delta modulator. After introduce some basic concepts of the sigma-delta modulator, we use DT-CT transformation to get available coefficients for the CT SDM. Then by the bibliography and discoveries during simulation, models about non-idealities, such as finite gain-bandwidth, excess loop delay, clock jitter, RC time-constant variation, coefficients variation, and R, C mismatches are built. Analysis in different structures also introduced: (1)2nd-order and 3rd-order modulators, (2)unit-delay and half-delay in the feed-back path, (3)summing circuit in CRFF modulator, and (4)CRFF and CRFB structures. Simulations here are using TSMC 0.18μm Mixed Signal 1P6M 1.8V process. The final CT SDM simulated specification is 250 kHz, 4mW, 83dB SNDR 3rd-order in CRFF form.